ActiveTest Memory Controller Runtime Error Detection
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Solution Overview
Problem
Large capacity digital memory circuits face manufacturing defects that are not immediately detectable, leading to reliability issues and potential system downtime due to double-bit errors, which existing Built-In Self-Test (BIST) and Built-In Self-Repair (BISR) systems struggle to address effectively.
Innovation Solution
The ActiveTest system provides proactive memory error hunting and runtime repair capabilities, integrating into memory controllers to test and correct errors deterministically with minimal software intervention, using a sliding window approach to minimize system downtime and optimize memory bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Built-In Self-Test (BIST) and Built-In Self Repair (BISR) systems are implemented, then memory reliability is improved, but subtle manufacturing defects that manifest later in time cannot be detected
Solution Approach 1:
The patent implements preliminary action by performing memory testing at multiple stages: during manufacturing (post-fabrication test), upon first power-up (power-up test), and periodically during operation (runtime testing). This multi-stage approach ensures that subtle defects are detected early when they manifest, preventing system failures later in the product lifecycle.
Solution Approach 2:
The patent employs feedback mechanisms through error detection and correction systems that continuously monitor memory operations during runtime. When errors are detected, the system provides feedback to correct them using error correction codes (ECC) or by marking affected memory locations, thereby maintaining reliability while detecting subtle defects that persist over time.
2Manufacturing precision
If memory testing is performed to detect defects, then manufacturing quality is improved, but system downtime increases due to testing requirements
Solution Approach 1:
The patent implements periodic action by scheduling memory tests at specific intervals during system operation rather than continuously. Runtime testing is performed periodically during normal operation, and power-up testing occurs at scheduled intervals after manufacturing. This periodic approach ensures quality detection while minimizing disruption to system functionality and reducing overall downtime.
Solution Approach 2:
The patent maintains continuity of useful action by designing testing mechanisms that operate alongside normal memory operations. Runtime error detection and correction continue during system operation without stopping productive work, and power-up tests are scheduled to minimize interruption. This ensures manufacturing quality is maintained while system downtime is minimized through continuous operational capability.
3Difficulty of detecting and measuring
If comprehensive memory testing is implemented, then defect detection capability is improved, but memory bandwidth usage increases
Solution Approach 1:
The patent applies partial action by implementing selective testing strategies that focus on detecting errors rather than performing exhaustive testing of all memory locations continuously. Runtime testing uses targeted error detection mechanisms (such as parity checks or CRC) that provide adequate defect detection capability without requiring comprehensive bandwidth consumption. Power-up testing performs more thorough checks but only when needed, balancing detection capability with bandwidth usage.
Data Source
AI summary
An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.