Actuator Data Transfer Scheduling for Storage Interface Balance
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Solution Overview
Problem
Data storage systems with multiple actuators face performance imbalances due to limited data paths, leading to idle data paths and inefficient data transfer rates, as each actuator is accessed separately and cannot utilize the shared interface simultaneously for read and write operations.
Innovation Solution
Implementing a method to schedule data transfer commands using specific rules for read and write operations, ensuring continuous data transfer by ensuring data availability in the buffer for read commands and available capacity for write commands, and dynamically balancing IOPS between actuators through logic stored in the system on a chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data transfer commands are scheduled separately for each actuator through a shared interface, then each actuator can be accessed individually, but the data path becomes idle and data transfer efficiency decreases
Solution Approach 1:
The patent merges read and write operations from multiple actuators into a single shared data path by implementing an arbitration mechanism that combines command queues from different actuators. The arbitration logic interleaves read and write commands across actuators, allowing the data path to continuously serve multiple actuators without idle periods, thus resolving the contradiction between individual access and transfer efficiency.
Solution Approach 2:
The patent introduces dynamic scheduling through an arbitration mechanism that adaptively selects which actuator receives data path access based on current buffer status, command type, and actuator readiness. This dynamic allocation allows the system to optimize data transfer efficiency in real-time while maintaining individual actuator access capability, preventing the data path from remaining idle.
2Device complexity
If the shared interface serves multiple actuators sequentially, then interface complexity is reduced, but data paths remain idle and throughput decreases
Solution Approach 1:
The patent implements periodic arbitration cycles that systematically switch between actuators serving read and write operations. The arbitration mechanism uses periodic time-division multiplexing to allocate data path access to different actuators in a structured sequence, ensuring that the shared interface maintains low complexity while maximizing throughput by eliminating idle periods through regular, predictable switching patterns.
3Reliability
If read and write operations are handled separately for each actuator, then operation reliability is improved, but data path utilization becomes unbalanced and performance decreases
Solution Approach 1:
The patent ensures continuous data path utilization by implementing an arbitration mechanism that maintains ready queues for both read and write operations from multiple actuators. The arbitration logic continuously selects available operations from these queues, ensuring the data path is always engaged in useful data transfer activities. This continuous operation maintains reliability through proper command handling while maximizing utilization by eliminating idle periods.
Data Source
AI summary
A method for scheduling data transfer commands between a first actuator or a second actuator across an interface is disclosed. The method includes balancing data transfer commands between the first actuator and the second actuator by applying a first rule for read commands and a second rule for write commands.