Acyclic Modeling of Combinational Loops via Edge-Sensitive Latches
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Solution Overview
Problem
Combinational loops in circuit designs lead to undesirable and unpredictable circuit behavior, including oscillations, due to their mutual dependence on zero delay semantics, making them difficult to handle in static scheduling and logic minimization, and existing solutions are either impractical for larger loops or require excessive computational resources.
Innovation Solution
Converting non-oscillatory combinational loops into acyclic circuits using edge-sensitive latches, which allows for modeling combinational loops as state-holding elements, breaking the loops and maintaining the original functionality without requiring finite state machines or retiming, with a linear-time complexity that scales efficiently for both small and large loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If combinational loops are used in circuit designs, then area optimization is achieved, but circuit behavior becomes unpredictable and oscillations occur
Solution Approach 1:
The patent extracts the problematic zero-delay feedback path from the combinational loop by introducing a latch element. This breaks the direct combinational loop while preserving the functional behavior, eliminating oscillations and unpredictable behavior while maintaining area efficiency.
Solution Approach 2:
The patent introduces a latch as an intermediary element between the feedback path elements. This latch mediates the feedback signal, providing a defined storage element that resolves the zero-delay conflict and stabilizes circuit behavior while maintaining the loop's functional purpose.
2Reliability
If combinational loops are converted to acyclic circuits using traditional methods, then circuit behavior stability is improved, but device complexity increases significantly
Solution Approach 1:
The patent segments the combinational loop into distinct functional portions by introducing a latch at a specific break point. This segmentation allows the loop to be transformed into an acyclic structure with controlled feedback, reducing complexity compared to complete loop elimination while maintaining stability.
Solution Approach 2:
The patent changes the temporal parameter of the feedback path by introducing a latch that holds the signal for one clock cycle. This parameter change transforms the zero-delay combinational loop into a structured feedback path with defined timing, improving stability without excessive complexity.
3Area of stationary object
If zero delay semantics are used in combinational loops, then area optimization is achieved, but handling in static scheduling and timing analysis becomes difficult
Solution Approach 1:
The latch serves as an intermediary that provides a clear temporal boundary in the feedback path. This intermediary element creates explicit timing relationships that are easily captured by static scheduling tools and timing analysis algorithms, eliminating the difficulties associated with zero-delay semantics.
Solution Approach 2:
The latch performs preliminary action by capturing and holding the feedback signal before it completes the loop. This preliminary storage action establishes a clear temporal order of operations, making the circuit amenable to static scheduling and timing analysis without requiring complex zero-delay resolution.
Data Source
AI summary
Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.