Successive-Approximation A/D Conversion With Multi-Timing Bit Comparison
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Solution Overview
Problem
Successive-approximation type A/D converters often produce gross errors due to incorrect high-order bit comparisons, especially when large noises are present in the input signal, and using a low-pass filter to mitigate this issue leads to delayed settling times and longer conversion times.
Innovation Solution
An A/D converter design that selects conversion bits from high-order to low-order, uses a threshold-value controlling section to determine boundary values, and employs multiple comparators to compare the input signal with analog threshold values at different timings, allowing for accurate bit determination without delaying the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low-pass filter with large capacity is added to remove instantaneous large noises, then measurement precision is improved, but conversion time increases due to delayed settling time
Solution Approach 1:
The patent performs preliminary comparison actions at multiple different timings within the conversion time interval. By comparing the analog input signal with the analog threshold value at several predetermined timings before final bit determination, the system gathers multiple comparison results to identify and eliminate erroneous comparisons caused by instantaneous noises, thereby achieving accurate conversion without requiring a low-pass filter that would extend the conversion time
Solution Approach 2:
The patent employs periodic comparison actions at multiple discrete timings (first timing, second timing, etc.) throughout the conversion time interval. This periodic sampling approach allows the system to capture the signal state at different moments, enabling detection and rejection of sporadic noise-induced erroneous comparisons while maintaining a fixed and relatively short overall conversion time
2Reliability
If multiple comparisons are performed at different timings, then reliability is improved by reducing noise impact, but device complexity increases
Solution Approach 1:
The patent makes the single comparator perform multiple comparison functions at different timings within the conversion time interval. The same comparator circuit is reused sequentially to generate multiple comparison results, eliminating the need for multiple parallel comparators. This multi-functional approach maintains high conversion reliability through multiple comparisons while avoiding the complexity and cost increase that would result from duplicating the comparator hardware
Solution Approach 2:
The patent discards erroneous comparison results that are identified as being caused by instantaneous noises and recovers the correct bit value by utilizing comparison results from other timings. The bit determining section selectively discards invalid data and recovers the accurate conversion result through logical processing of multiple comparison outcomes, thereby maintaining high reliability without requiring redundant hardware components
Data Source
AI summary
There is provided an A/D converter that outputs a digital output signal obtained by digitalizing an analog input signal. The A/D converter includes a bit selecting section that selects a conversion object bit from a high-order bit to a low-order bit of the digital output signal in order, a threshold-value controlling section that determines a threshold data expressing a boundary value between zero and one of the conversion object bit, a D/A converting section that digital-to-analog converts the threshold data and generates an analog threshold value, a comparing section that compares, at a plurality of different timings in a conversion time interval determining a value of the conversion object bit, the analog input signal and the analog threshold value and outputs a plurality of comparison results at the timings, and a bit determining section that determines the value of the conversion object bit.