AD Conversion Device Bit-Memory Scanning for Transmission Efficiency
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Solution Overview
Problem
Existing analog-to-digital (AD) conversion devices face challenges in increasing digital signal transmission rates without a corresponding increase in the number of transmission lines, which affects the efficiency and speed of data processing in imaging systems.
Innovation Solution
The proposed solution involves an AD conversion device with a comparator, bit-memories, an output circuit, and scanning circuits that selectively connect and transmit bit signals, reducing the load on transmission lines and enhancing serial transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bit-memories are connected to common transmission lines, then the number of transmission lines is reduced, but the transmission rate of digital signals decreases due to increased load and parasitic capacitance
Solution Approach 1:
The patent divides the bit-memories into multiple groups, with each group connected to a separate transmission line. This segmentation allows parallel transmission of bit signals from different groups, thereby maintaining high transmission rates while reducing the total number of transmission lines needed compared to connecting each bit-memory individually.
Solution Approach 2:
The patent employs scanning circuits that sequentially select and activate different groups of bit-memories in periodic time slots. This periodic activation allows multiple bit-memories to share common transmission lines without signal conflict, achieving high transmission rates through time-division multiplexing while minimizing the number of physical transmission lines required.
2Device complexity
If multiple bit-memories are connected to common transmission lines, then device complexity is reduced, but parasitic capacitance increases, affecting signal integrity
Solution Approach 1:
The patent segments bit-memories into multiple groups connected to different transmission lines, which distributes the parasitic capacitance load across multiple lines rather than concentrating it on a single common line. This reduces the parasitic capacitance effect on each individual transmission path.
Solution Approach 2:
By sequentially activating different groups of bit-memories in periodic time slots through scanning circuits, the patent ensures that only one group drives each transmission line at any given time. This time-division approach minimizes the cumulative parasitic capacitance effect while maintaining simple connection structures.
Data Source
AI summary
Provided is an analog-to-digital (AD) conversion device including: a comparator configured to compare an input analog signal and a reference signal; a plurality of first bit-memories configured to hold a digital signal including a plurality of bits generated based on a result of comparison performed by the comparator, each of the plurality of first bit-memories holding a bit signal of a corresponding one bit among the plurality of bits of the digital signal; an output circuit to which the bit signal output from each of the plurality of first bit-memories is commonly input; a transmission line configured to transmit the bit signal output from the output circuit; and a first scanning circuit configured to sequentially select, from the plurality of first bit-memories, a first bit-memory that outputs the bit signal to the output circuit.