AD Conversion Circuit Noise Error Reduction
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Solution Overview
Problem
The existing TDC type AD conversion circuits using asymmetry type oscillation circuits are prone to errors due to noise interference, leading to incorrect encoding values when detecting logic states of lower phase signals, resulting in significant errors in the AD conversion process.
Innovation Solution
The proposed AD conversion circuit includes a reference signal generation unit, a comparison unit, a clock generation unit with a delay circuit, a latch unit, and an encoding unit that performs detection and encoding operations based on the logic states of lower phase signals, allowing for precise detection of both consecutive and nonconsecutive logic states, thereby reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If noise interference is present in the detection of logic states of lower phase signals, then the AD conversion circuit can operate, but encoding errors occur leading to significant conversion errors
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit monitors the logic states of lower phase signals and provides feedback to the encoding circuit. When noise causes incorrect logic state detection, the feedback system enables error correction by comparing detected states with expected sequences, thereby maintaining reliable AD conversion despite noise interference.
Solution Approach 2:
The patent introduces an intermediary detection circuit between the VCO and the encoding circuit. This detection circuit acts as a mediator that verifies the logic states of lower phase signals before they are encoded. By inserting this intermediary layer, the system can identify and correct noise-induced errors in logic state detection, preventing encoding errors.
2Device complexity
If the detection circuit only detects consecutive logic states, then the circuit structure is simple, but encoding errors occur due to noise interference
Solution Approach 1:
The patent segments the detection process into multiple independent detection units, each responsible for detecting specific logic state patterns. Instead of a single complex detection circuit, multiple simpler detection circuits work in parallel to monitor different aspects of the lower phase signals. This segmentation allows the system to detect both consecutive and non-consecutive logic states, improving encoding accuracy without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent implements partial detection of logic states by focusing on detecting specific critical patterns rather than all possible states. The detection circuit performs selective monitoring of logic state transitions, detecting only the essential patterns needed for accurate encoding. This partial action approach maintains relatively simple circuit structure while achieving sufficient encoding accuracy by concentrating detection resources on the most critical signal transitions.
3Speed
If the AD conversion circuit uses a TDC type with asymmetry oscillation circuit, then the conversion speed is high, but noise interference causes significant conversion errors
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit monitors the logic states of lower phase signals and provides feedback to the encoding circuit. When noise causes incorrect logic state detection, the feedback system enables error correction by comparing detected states with expected sequences, thereby maintaining reliable AD conversion despite noise interference.
Solution Approach 2:
The patent introduces an intermediary detection circuit between the VCO and the encoding circuit. This detection circuit acts as a mediator that verifies the logic states of lower phase signals before they are encoded. By inserting this intermediary layer, the system can identify and correct noise-induced errors in logic state detection, preventing encoding errors.
Data Source
AI summary
An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.


