A-D Conversion Clock Circuit Using Transistor Ratio Delays
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Solution Overview
Problem
The challenge lies in constructing a clock generation circuit for A-D conversion circuits that can function effectively as design rules shrink, particularly due to difficulties in varying transistor gate widths and constructing sampling clock generation circuits using FinFETs or planar transistors during miniaturization.
Innovation Solution
The A-D conversion circuit employs a clock generation circuit with inverters having different ratios of n-channel and p-channel transistors connected in common-gate and parallel-connection manners, allowing for the generation of sampling clocks with varying edge timings, facilitating the construction of clock generation circuits even under shrinking design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If design rules are shrunk for miniaturization, then device integration is improved, but construction of sampling clock generation circuits becomes difficult due to inability to vary transistor gate widths
Solution Approach 1:
The patent changes the electrical parameters of the inverter circuit by varying the number ratio between n-channel and p-channel transistors connected in common-gate parallel configuration. This allows different clock edge timings to be generated without relying on gate width variation, thus enabling clock generation circuit construction even when design rules are shrunk and transistor gate width control becomes difficult.
2Reliability
If FinFETs or planar transistors are used during miniaturization, then device functionality is maintained, but variation in transistor characteristics increases making clock generation difficult
Solution Approach 1:
Instead of controlling transistor characteristics through gate width (which becomes imprecise during miniaturization), the patent uses parameter changes in the transistor count ratio of parallel-connected common-gate structures. This approach is less sensitive to characteristic variations and maintains manufacturing precision even when using FinFETs or planar transistors at scaled dimensions.
Solution Approach 2:
The patent merges multiple transistors in parallel common-gate configuration to create inverter stages with different effective drive strengths. By combining transistors in this manner, the circuit achieves the desired clock edge timing variation while being more tolerant of individual transistor characteristic variations that occur during miniaturization.
3Productivity
If multiple delay units are connected in series for pulse delay, then A-D conversion function is achieved, but circuit complexity increases
Solution Approach 1:
The inverter circuit with variable n-channel to p-channel transistor ratios serves multiple functions: it acts as a delay element in the pulse delay chain and simultaneously generates sampling clocks with different edge timings. This multi-functionality reduces the need for separate clock generation circuits, thereby reducing overall circuit complexity while maintaining A-D conversion capability.
Data Source
AI summary
An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.