Ramp Run-Up AD Conversion Circuit Clock Frequency Management
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Solution Overview
Problem
The increasing number of pixels and frame rate in digital still cameras and cellular phones leads to high clock frequencies and power consumption issues in column AD conversion circuits, making it difficult to generate and distribute clock signals effectively, resulting in reduced bit accuracy and increased power consumption.
Innovation Solution
Incorporating latches in AD conversion circuits to hold clock signals or their converted values, allowing for higher bit widths without increasing clock frequency, and using Gray code or phase shift code to minimize sampling errors and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of pixels and frame rate are increased, then the processing speed and image quality are improved, but the clock frequency and power consumption increase making it difficult to generate and distribute clock signals effectively
Solution Approach 1:
The patent divides the AD conversion process into multiple stages using latches. The first latch holds the clock signal at a specific phase, while the second latch holds the converted value. This segmentation allows the system to process multiple pixels per clock cycle without increasing the overall clock frequency, thereby maintaining power efficiency while improving processing speed.
Solution Approach 2:
The patent uses latches to preliminarily hold the clock signal and converted values at specific phases before the next conversion cycle begins. This preliminary action ensures that all necessary data is prepared and held ready, allowing parallel processing of multiple pixels without requiring higher clock frequencies, thus avoiding increased power consumption.
2Measurement precision
If higher bit widths are used without increasing clock frequency, then bit accuracy is improved, but latches are required to hold clock signals or converted values
Solution Approach 1:
The patent introduces latches as intermediary elements between the comparator and the output register. These latches hold the converted values temporarily, allowing the system to achieve higher bit accuracy by performing multiple conversion cycles at the same clock frequency. The latches act as buffers that manage the complexity of high-bit-width conversions without requiring higher clock speeds.
3Loss of energy
If Gray code or phase shift code is used, then sampling errors are minimized and power consumption is reduced, but code conversion circuits are required
Solution Approach 1:
The patent changes the parameter of code representation from binary to Gray code or phase shift code. This parameter change reduces power consumption because Gray code transitions involve only one bit changing at a time, minimizing switching activity. The code conversion circuits required are relatively simple compared to the power savings achieved, making this an effective trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed processing with high picture quality by lowering the maximum clock frequency, improving bit accuracy, and reducing power consumption, while maintaining conversion time and accuracy.
Implementation Method 1
photoelectric conversion elements arranged in the form of a matrix
Data Source
AI summary
In a solid state imaging device to be included in an imaging device such as a digital camera, a ramp run-up AD conversion circuit for AD converting a pixel signal is provided corresponding to one or a plurality of pixel columns. A column counter provided in each ramp run-up AD conversion circuit holds an upper bit, and a clock signal is supplied to one or plural latches for holding a lower bit. Thus, fast and accurate AD conversion can be realized while suppressing increase of clock frequency.