A/D Conversion Circuit Count Clock Switching Error Prevention
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Solution Overview
Problem
Conventional A/D conversion circuits in image pick-up devices suffer from erroneous counting due to count clock switching, particularly in the transition from a high to a low state, leading to inaccuracies in digital data acquisition.
Innovation Solution
The proposed A/D conversion circuit incorporates a ring-like delay circuit, a latch unit, and binary counters with a data protection function to prevent erroneous counting by switching the count clock input between different output signals from the delay circuit, ensuring accurate counting and data protection during clock transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If count clock switching is performed in conventional A/D conversion circuits, then the counting operation can be maintained, but erroneous counting occurs during the transition from high to low state
Solution Approach 1:
The patent applies preliminary action by performing data protection of the upper counter value immediately before the count clock switching occurs. The control signal generation unit generates a data protection signal in advance based on the timing of the count clock switching signal, ensuring that the upper counter is protected from erroneous counting before the harmful transition happens.
Solution Approach 2:
The patent uses a data protection signal as an intermediary between the count clock switching signal and the upper counter. This control signal acts as a mediator that prevents the direct harmful effect of clock switching on the counter operation, by enabling the upper counter only when the data protection signal is active.
2Productivity
If the upper counter operates during count clock switching, then counting continuity is maintained, but measurement precision deteriorates due to erroneous counts
Solution Approach 1:
The control signal generation unit performs preliminary action by generating the data protection signal before the count clock switching occurs. This allows the upper counter to be properly protected in advance, maintaining counting continuity while preventing measurement errors during the critical transition period.
Solution Approach 2:
The patent implements feedback by using the count clock switching signal to generate the data protection signal, which then controls the operation of the upper counter. The control signal generation unit continuously monitors the clock switching signal and adjusts the data protection signal accordingly, creating a feedback loop that maintains precision while preserving counting continuity.
Data Source
AI summary
An A/D conversion circuit includes a reference signal generation unit, a comparison unit, a delay circuit, a latch unit, an arithmetic circuit, a lower counter, and an upper counter including a second binary counter performing counting using the count clock based on one of the output signals constituting the first lower phase signal, performs counting to acquire a first upper count value, inverts values of respective bits constituting the first upper count value, performs counting using the count clock based on of the output signals constituting the second lower phase signal, and performs counting based on the second upper count clock to acquire a second upper count value, and having a data protection function for protecting an upper count value held by the second binary counter at a time of count clock switching, wherein digital data corresponding to a difference between the first and second analog signals is acquired.