AD Conversion Circuit Latch Timing Control for Power Reduction

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Solution Overview

Problem

The existing analog-to-digital (AD) conversion circuits in solid-state imaging devices consume high current due to continuous operation of latch circuits during AD conversion, especially at high pixel counts and frame rates, leading to increased power consumption and heat generation.

Innovation Solution

The proposed AD conversion circuit includes a reference signal generation section, a comparison section, a first count section, a latch section, and a latch control section that enables the latch section only during specific timing intervals, allowing it to operate from the start of the comparison process to a delayed second timing, thereby reducing the operational period of the latch circuits and minimizing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the latch circuits continuously operate during the entire AD conversion period, then the count values can be latched without loss, but the current consumption increases significantly

Engineering Contradiction:
Improvelatch operation reliabilityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The latch circuits are enabled only during specific periodic intervals (first timing to second timing) rather than continuously operating. The latch control section controls the latch circuits to operate only when needed for latching count values, creating a periodic on-off pattern that reduces energy consumption while maintaining reliability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The operational state of the latch circuits is dynamically changed from static continuous operation to dynamic periodic operation. The latch control section dynamically enables and disables the latch circuits based on the timing requirements of the AD conversion process, optimizing both reliability and energy efficiency.

Inventive Principle:
Principle #15Dynamics

2Productivity

If the latch section operates for a longer duration, then more count values can be captured, but the power consumption and heat generation increase

Engineering Contradiction:
Improvecount value capture capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The latch section operates periodically only during the critical timing window when count values need to be captured. By limiting operation to the period from first timing to second timing, the system maintains productivity for capturing necessary count values while minimizing energy loss during non-critical periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The operational parameters of the latch section are changed by controlling the enable/disable timing. The latch control section adjusts the operational window parameters (start time, end time) to match the actual needs of the AD conversion process, optimizing the balance between productivity and energy efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8625015B2AD conversion circuit and solid-state imaging apparatus
Publication Date: 2014.01.07 OLYMPUS CORPORATION(JP)
  • US8625015B2 patent drawing
  • US8625015B2 patent drawing
  • US8625015B2 patent drawing

AI summary

A comparison section includes an analog signal to be subjected to AD conversion to a reference signal that increases or decreases with the passage of time, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A first count section counts a clock signal of a predetermined frequency as a count clock and outputs a count value. A latch section latches the count value output from the first count section. A latch control section enables the latch section at a first timing related to an end of the comparison process and causes the latch section to execute a latch operation at a second timing delayed by a predetermined time from the first timing.