Dual-Comparator AD Conversion Circuit for Voltage Bounce Stability
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Solution Overview
Problem
Conventional tdcSS type AD conversion circuits in solid-state image pickup devices suffer from reduced AD conversion accuracy due to power and ground voltage bounce, particularly in central columns where wiring resistance causes voltage drops, leading to transient currents and timing variations that affect latch operations.
Innovation Solution
The AD conversion circuit incorporates a dual comparison circuit structure with a main and sub-comparison circuit, along with a clock generation unit and latch units, where the latch circuits operate differently based on phase signals to manage timing and reduce current consumption, eliminating the need for an inversion delay circuit and minimizing voltage bounce effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional tdcSS type AD conversion circuit is used, then the circuit structure is simple, but the AD conversion accuracy deteriorates due to power and ground voltage bounce in central columns
Solution Approach 1:
The comparison unit is divided into a first comparison circuit and a second comparison circuit that operate at different timings. The first comparison circuit performs comparison at a first timing, while the second comparison circuit performs comparison at a second timing that is earlier than the first timing. This segmentation allows the circuit to avoid the period when voltage bounce occurs, thereby maintaining AD conversion accuracy without requiring a completely redesigned complex circuit structure.
Solution Approach 2:
The second comparison circuit performs the comparison operation in advance (at an earlier timing) before the voltage bounce occurs in the power and ground lines. By completing the comparison before the harmful voltage fluctuation happens, the circuit ensures accurate measurement without needing additional complex compensation mechanisms.
2Reliability
If latch circuits operate simultaneously across all columns, then the operation is simple, but transient currents cause voltage bounce and timing variations
Solution Approach 1:
The latch circuits are configured to operate periodically at different timings for different columns. Specifically, the first latch circuit operates at a first timing while the second latch circuit operates at a second timing. This staggered periodic operation prevents simultaneous switching across all columns, thereby reducing transient current peaks and voltage bounce while maintaining reliable latch operations.
Solution Approach 2:
The second latch circuit is configured to complete its operation in advance before the first latch circuit operates. By performing the latch operation earlier, the circuit avoids the period when voltage bounce occurs due to simultaneous operations, thereby ensuring stable and reliable latch operations without requiring excessive current management complexity.
3Measurement precision
If an inversion delay circuit is used to control latch timing, then the timing control is precise, but the circuit complexity increases and current consumption rises
Solution Approach 1:
The invention extracts and eliminates the inversion delay circuit from the circuit structure. Instead of using a separate inversion delay circuit to control latch timing, the design directly configures the first and second latch circuits to operate at different timings through their respective comparison circuits. This removal simplifies the circuit structure while maintaining precise timing control through the inherent timing differences in the comparison operations.
4Ease of manufacture
If wiring resistance is present in central columns, then the device can be manufactured, but voltage drops cause transient currents and timing variations
Solution Approach 1:
The comparison and latch operations are configured to complete before the voltage drop and transient current effects become significant in the central columns. By performing the critical measurements and state captures in advance, the circuit ensures accurate AD conversion despite the presence of wiring resistance and resulting voltage drops that cannot be eliminated in manufactured devices.
Data Source
AI summary
An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.