A/D Converter Using Dummy Capacitor for Offset Calibration
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Solution Overview
Problem
Successive approximation A/D converters face limitations in achieving high resolution due to comparator offset errors and manufacturing variations, particularly in self-calibration techniques, which affect accuracy and require additional fabrication steps increasing costs.
Innovation Solution
The A/D converter design incorporates a capacitive DAC, a resistive DAC, and a resistive correction DAC with a comparator having differential circuits to minimize comparator offset and measure capacitor mismatch accurately, using interconnect layers for capacitive elements and resistive elements to reduce parasitic capacitance and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If self-calibration techniques are used to achieve higher resolutions (14 bits and higher), then resolution is improved, but comparator offset errors cause inaccurate measurement of capacitor mismatch, limiting accuracy
Solution Approach 1:
A dummy capacitor is introduced as an intermediary element to measure capacitor mismatch separately from the main capacitive DAC. The dummy capacitor allows accurate measurement of mismatch by providing a reference that is not affected by the comparator offset during the measurement process, thereby resolving the accuracy limitation caused by comparator offset errors in self-calibration techniques
Solution Approach 2:
The measurement function is segmented from the main conversion function by using a separate dummy capacitor dedicated to mismatch measurement. This segmentation allows the measurement process to be independent of the comparator offset issues that affect the main capacitive DAC during conversion, enabling accurate calibration without compromising conversion accuracy
2Measurement precision
If PIP capacitors or MIM capacitors are used to reduce voltage dependence for 14-bit or higher resolution, then resolution is improved, but additional fabrication steps are required, increasing manufacturing cost
Solution Approach 1:
The invention uses standard MOS capacitors instead of expensive PIP or MIM capacitors for the dummy capacitor and other non-critical capacitive elements. While MOS capacitors have higher voltage dependence, this is acceptable for the dummy capacitor since it is only used for mismatch measurement and not for the final conversion process, thereby reducing manufacturing cost without compromising the 14-bit resolution achievement
3Speed
If coupling capacitors are formed from MIM capacitors to reduce parasitic capacitance in the comparator, then speed is improved, but additional fabrication steps are required, increasing manufacturing cost
Solution Approach 1:
Different capacitor types are used in different locations based on specific requirements: MIM capacitors are used only where low parasitic capacitance is critical (such as coupling capacitors in the comparator path), while standard MOS capacitors are used elsewhere. This localized application of high-performance components achieves the necessary speed improvement without incurring the cost of using MIM capacitors throughout the entire circuit
Data Source
AI summary
An A/D converter includes a capacitive DAC configured to perform conversion of high-order bits by receiving a differential signal, a resistive DAC configured to perform conversion of low-order bits, a resistive correction DAC configured to operate to correct the capacitive DAC, and a comparator. The capacitive DAC includes a positive-side capacitive DAC and a negative-side capacitive DAC operating in a complementary fashion, and the comparator, which includes a plurality of differential circuits, is configured to compare output potentials of the positive-side capacitive DAC and the negative-side capacitive DAC. The positive-side capacitive DAC and the negative-side capacitive DAC include first capacitive elements each formed from interconnect layers excluding an uppermost interconnect layer, and the comparator includes second capacitive elements each provided between adjacent ones of the differential circuits and formed from interconnect layers including the uppermost interconnect layer.