A/D Converter with Separate Sampling Capacitor for Wider Input Range
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Solution Overview
Problem
Conventional A/D converters face limitations in efficiently converting analog signals to digital values, particularly in handling high-voltage inputs and maintaining operation speed while expanding input range, due to shared sampling and integration capacitors which restrict sampling periods and require high output impedance from input sources.
Innovation Solution
The proposed A/D converter design incorporates a sampling capacitor independent of integration capacitors, with a charge subtraction unit and a sub-A/D converter, allowing for parallel operation and independent sampling, thereby widening the input range and improving processing speed by enabling arbitrary voltage settings and reliable sampling even with low current supply capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared sampling and integration capacitor is used, then the circuit complexity is reduced, but the sampling period is restricted and the input range cannot be expanded
Solution Approach 1:
The patent divides the capacitor function into separate sampling capacitor and integration capacitor, allowing independent operation of sampling and integration processes. This segmentation enables the sampling capacitor to be optimized for high-voltage sampling while the integration capacitor handles precision integration, thereby expanding the input range without increasing overall circuit complexity.
2Device complexity
If a shared sampling and integration capacitor is used, then the circuit structure is simplified, but the processing speed is limited
Solution Approach 1:
By separating the sampling capacitor from the integration capacitor, the patent enables parallel operation where sampling can occur independently of the integration process. This allows the sampling phase to complete quickly without waiting for integration cycles, thereby increasing processing speed while maintaining a relatively simple circuit structure.
Solution Approach 2:
The patent implements distinct sampling periods and integration periods through periodic switching control. The sampling capacitor operates during designated sampling windows independent of the continuous integration process, enabling higher sampling rates and improved processing speed without complicating the circuit structure.
3Device complexity
If the sampling capacitor is shared with integration capacitor, then the circuit design is simplified, but high output impedance is required from input sources
Solution Approach 1:
The patent separates the sampling capacitor from the integration capacitor, allowing the sampling capacitor to be directly connected to the input source during sampling periods. This independent connection enables the sampling capacitor to capture high-voltage signals directly without being constrained by the integration capacitor's impedance requirements, thereby reducing the output impedance requirement from input sources.
4Device complexity
If sequential charge subtraction is performed, then the circuit operation is simplified, but the conversion time increases
Solution Approach 1:
The patent implements periodic charge subtraction operations synchronized with the sampling and integration cycles. By performing charge subtraction at optimized intervals rather than continuously or solely sequentially, the patent reduces the total conversion time while maintaining relatively simple circuit operation through periodic switching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances processing speed and expands the input range, allowing for reliable sampling and conversion of high-voltage signals while reducing the requirement for high output impedance from input sources, thus providing an efficient and flexible A/D conversion solution.
Implementation Method 1
a sampling capacitor independent of integration capacitors
Implementation Method 2
an integrator including an operational amplifier
Implementation Method 3
an integration capacitor provided between a first input terminal and an output terminal of the operational amplifier
Data Source
AI summary
An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits. A sum of the most significant bits and the least significant bits are output as an output signal. Initialization of the charge of the integration capacitor, the charge transfer operation for a next A/D conversion, and generation of the most significant bits are performed in parallel with the A/D conversion in the sub-A/D converter after the generation of the most significant bits.