A/D Converter Sequencing with Ordered Result Register Access
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Solution Overview
Problem
Conventional A/D conversion devices lack flexibility in sequencing analogue signal conversion, require significant software processing for timing control, and impose restrictions on reading conversion results, especially when dealing with multiple sensors and urgent input signals.
Innovation Solution
An A/D conversion device with a conversion sequence setting register that allows flexible ordering of signal conversion, a multiplexer for sequential signal selection, and a conversion result register with storage regions for ordered digital signal storage, along with a back-up register to save data, reducing software processing load and allowing unrestricted reading of results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional A/D conversion devices use fixed scanning mode or select mode, then the conversion process is simple to implement, but the flexibility in sequencing analogue signal conversion is limited
Solution Approach 1:
The conversion sequence setting register is divided into multiple regions, with each region corresponding to a specific input channel. This segmentation allows independent configuration of conversion sequences for different channels, providing flexibility in sequencing while maintaining a structured and manageable register organization that doesn't overly complicate the device.
Solution Approach 2:
The patent introduces dynamic conversion sequencing capability where the conversion order can be flexibly changed by programming the conversion sequence setting register. This allows the system to adapt conversion sequences based on application requirements, transitioning from fixed static modes to dynamic reconfigurable sequences without requiring complete hardware redesign.
2Adaptability or versatility
If software processing is used to control conversion timing in conventional devices, then some flexibility is achieved, but the software processing load increases significantly
Solution Approach 1:
The conversion control unit automatically generates conversion timing signals based on the conversion sequence setting register configuration. The system serves itself by internally managing the conversion timing and sequencing without requiring external software intervention for each conversion operation, thereby reducing software processing load while maintaining flexibility through hardware-based automatic sequencing.
Solution Approach 2:
The patent replaces software-based timing control with a hardware-based conversion control unit that automatically manages conversion sequencing. This substitution transfers the timing control function from the software domain to the hardware domain, eliminating the need for software to generate timing signals and reducing the software processing burden.
3Productivity
If conventional devices read conversion results sequentially, then the device structure is simple, but the reading process is restricted and less efficient
Solution Approach 1:
The conversion result register is segmented into multiple storage regions, with each region corresponding to a specific input channel. This segmentation allows selective reading of conversion results from different channels independently, enabling efficient data access without requiring sequential reading of all channels, thus improving productivity while maintaining a structured register organization.
Solution Approach 2:
The patent introduces a new dimension of data access by organizing conversion result storage in a multi-region structure that allows parallel or selective reading operations. This dimensional organization of storage regions enables efficient reading of specific conversion results without affecting other channels, enhancing reading efficiency without proportionally increasing device complexity.
4Reliability
If the same analogue input signal is converted multiple times in conventional devices, then continuous monitoring is possible, but significant time is wasted converting unrequired signals
Solution Approach 1:
The conversion sequence setting register enables dynamic configuration of conversion sequences, allowing the system to prioritize and repeat conversion of specific important channels while reducing or eliminating conversions of less critical channels. This dynamic sequencing capability provides continuous monitoring of required signals without wasting time on unnecessary conversions, improving time efficiency while maintaining reliability for critical signals.
Data Source
AI summary
In a scanning mode: a conversion sequence setting register sets the sequence in which analogue signals are to be converted; a multiplexer selects a single analogue signal sequentially from a plurality of analogue signals, in accordance with the order that is set in this conversion sequence setting register; an A/D converter converts the analogue signal selected by this multiplexer to a digital signal; a conversion result register having a plurality of result registers stores the digital signal obtained by conversion by the A/D converter in these storage regions in the order in which conversion was effected; and a back-up register includes result registers respectively corresponding to this plurality of result registers.