Parallel A/D Converter Timing Control for Power Supply Noise Isolation

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Solution Overview

Problem

Noise generated in one A/D converter is propagated to another through a common analog power supply, significantly deteriorating conversion precision in microcomputers with multiple parallel analog circuits.

Innovation Solution

Implementing a timing control mechanism where the operation start of one analog circuit is synchronized with the operation cycle of another, using timing control data to suppress or delay the start of analog operations in other circuits, thereby preventing noise propagation through the analog power channel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple A/D converters operate in parallel with asynchronous timing, then conversion throughput is improved, but noise propagates through the common analog power supply and conversion precision deteriorates

Engineering Contradiction:
Improveconversion throughputVSAvoidconversion precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements periodic synchronous operation of multiple A/D converters by introducing a timing control mechanism that coordinates the start timing of each converter. The timing control circuit generates start signals at predetermined intervals, ensuring that converters operate in synchronized periodic cycles rather than asynchronously, thereby preventing noise propagation while maintaining efficient parallel conversion throughput

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent introduces a timing control circuit as an intermediary component that mediates between the parallel A/D converters and the common analog power supply. This intermediary circuit synchronizes the operation timing of multiple converters, preventing direct noise coupling through the power supply while allowing parallel operation to continue

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If multiple A/D converters are coupled to a common analog power supply terminal, then device complexity is reduced and integration is improved, but noise from one converter propagates to others through the power supply channel

Engineering Contradiction:
Improvepower supply configuration complexityVSAvoidnoise propagation
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by synchronizing the start timing of multiple A/D converters before noise propagation can occur. The timing control circuit预先 (in advance) coordinates the operation cycles of all converters, ensuring that switching operations occur at predetermined synchronized moments rather than randomly, thereby preventing noise coupling through the common power supply

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements preliminary anti-action by introducing a timing control mechanism that preemptively prevents noise propagation. By controlling the start timing of each converter based on synchronized periodic cycles, the system anticipates and prevents noise coupling before it can occur, rather than attempting to filter or mitigate noise after it has propagated

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS8593322B2Microcomputer, semiconductor device, and microcomputer applied equipment
Publication Date: 2013.11.26 RENESAS ELECTRONICS CORP
  • US8593322B2 patent drawing
  • US8593322B2 patent drawing
  • US8593322B2 patent drawing

AI summary

In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing control data that specifies an interval for suppressing the analog operation start of the one analog circuit in the analog operation cycle of the other analog circuit that has already started the analog operation. The control is conducted so that when the operation of one analog circuit starts, timing when the operation of the one analog circuit is influenced by the analog operation start of the other analog circuits in the operation cycle of the one analog circuit is retained as timing control data in advance, and the analog operation start of the other analog circuits is delayed or temporarily suppressed in synchronization with the operation start of the one analog circuit according to the timing control data.