N-Bit A/D Conversion Hysteretic Control for 1-Bit Jitter
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Solution Overview
Problem
Existing analog-to-digital converters experience 1-bit jitter or oscillation in output signals when the analog input has noise or the digital signal is on the edge of a bit transition, making it difficult to remove this oscillation without reducing conversion resolution or increasing the number of bits.
Innovation Solution
The implementation of an N-bit analog-to-digital converter using 2N 1-bit conversion stages and an arithmetic logic unit (ALU) that compares new digital signals with previous outputs, determining whether to update the digital output based on differences and trends, or using an M-bit storage unit to calculate and compare sums of recent digital signals to select the appropriate output, effectively eliminating oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional N-bit A/D conversion is used, then conversion resolution is maintained, but 1-bit jitter or oscillation occurs in the output signal when noise is present or during bit transitions
Solution Approach 1:
The patent introduces a digital filter as an intermediary component between the parallel A/D converters and the final output. This filter processes the digital signals from multiple converters and produces a stabilized output, eliminating the 1-bit jitter while preserving the original conversion resolution. The digital filter acts as a mediator that smooths out oscillations without requiring additional quantization bits.
2Reliability
If filtering methods are applied to remove oscillation, then output stability improves, but conversion resolution is sacrificed
Solution Approach 1:
The patent divides the A/D conversion process into multiple parallel 1-bit conversion stages (2N stages for N-bit output). Each stage independently converts the analog signal, and their results are combined through digital filtering. This segmentation allows the system to achieve stable output through the filtering of multiple coarse measurements rather than relying on a single high-resolution conversion, thereby maintaining overall resolution while improving stability.
3Reliability
If the number of output bits is increased to reduce oscillation, then output stability improves, but device complexity increases
Solution Approach 1:
The patent employs dynamic element matching and sequential comparison techniques where the relative weighting of conversion stages is adjusted based on the current conversion state. The system dynamically selects and weights specific 1-bit converter outputs during the conversion process, allowing stable N-bit output without requiring excessive total bits or static oversampling. This dynamic approach reduces the total number of converters needed compared to static redundancy methods.
Data Source
AI summary
The present invention introduces methods to eliminate 1-bit jitter problem in the N-bit A/D conversion applications. The methods do not require any increase in the total bit of A/D conversion.