AD Conversion Ramp Control for Faster Comparator Reset
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Solution Overview
Problem
Existing analog-to-digital (AD) conversion techniques have a room for reducing the AD conversion period and comparator reset period, as the voltage range of the reference signal from a predetermined potential to the comparator reset potential does not effectively utilize the signal output change region, leading to inefficiencies in the conversion process.
Innovation Solution
The proposed AD conversion circuit employs a ramp signal with two change rates, initially changing at a first rate and then at a second, smaller rate, allowing for a third potential to be input to the comparator before resetting, thereby optimizing the AD conversion period and reducing the comparator reset period by utilizing a region with excellent linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the reference signal changes potential from a predetermined potential to a comparator reset potential at a constant rate, then the AD conversion process is simple, but the voltage range does not effectively utilize the signal output change region, leading to longer conversion time
Solution Approach 1:
The ramp signal generation circuit dynamically changes the change rate of the reference signal during the conversion process. Specifically, the circuit switches between a first change rate (when the ramp signal potential is below the third potential) and a second change rate (when the ramp signal potential is at or above the third potential), allowing optimal utilization of the comparator's signal output change region while maintaining manageable circuit complexity through controlled dynamic behavior.
Solution Approach 2:
The invention changes the parameter of the ramp signal's change rate during the conversion process. By adjusting the change rate parameter based on the ramp signal's current potential level (using a faster rate below the third potential and a slower rate at or above it), the system optimizes the utilization of the comparator's linear region, thereby reducing the overall conversion time without requiring fundamentally new circuit architectures.
2Productivity
If the comparator is reset at a higher potential to reduce reset period, then the conversion speed improves, but the linearity of the ramp signal in the conversion region may be compromised
Solution Approach 1:
The invention applies different change rates to different regions of the ramp signal's potential range. A first (faster) change rate is applied when the potential is below the third potential, and a second (slower) change rate is applied when the potential is at or above the third potential. This local differentiation ensures that the critical conversion region maintains excellent linearity for accurate conversion, while still achieving high productivity by utilizing faster rates in other regions and optimizing the overall conversion process.
Data Source
AI summary
An AD conversion circuit includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a result of the comparison, and performs an AD conversion using the comparison result signal. In the comparison, a potential of the ramp signal changes with a lapse of time from a first potential to a second potential. Before the comparison, the potential of the ramp signal changes at a first change rate and then changes at a second change rate smaller than the first change rate, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and the comparator is reset in a state where the third potential is input to the comparator.