A/D Readout Circuit With Multi-Sampling for Low-Noise Wide Dynamic Range

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Solution Overview

Problem

Current CMOS image sensors face challenges in achieving both high sensitivity and low noise while maintaining a wide dynamic range, as simple amplification methods fail to generate the required gradation for A/D conversion and ensure both high sensitivity/low noise and wide dynamic range performance.

Innovation Solution

An A/D converter and readout circuit that perform multiple-times sampling and integration of signals with reversed polarity, using operational amplifiers and capacitors to enhance the signal-to-noise ratio by multiplying the signal component by N and random noise by sqrt(N), thereby improving the S/N ratio and achieving a wide dynamic range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If simple amplification is used to reduce noise, then noise is reduced, but dynamic range cannot be obtained and required gradation for A/D conversion cannot be generated

Engineering Contradiction:
ImprovenoiseVSAvoiddynamic range
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent divides the amplification process into multiple stages with different gain levels. The first amplification stage provides high gain for noise reduction, while the second amplification stage provides additional gain levels to extend dynamic range. This segmentation allows the system to achieve both noise reduction and wide dynamic range by processing signals through different amplification paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic gain switching where the amplification factor can be changed based on signal conditions. The amplifier can switch between different gain levels (first amplification factor and second amplification factor) to adapt to varying signal requirements, enabling both high-sensitivity low-noise operation and wide dynamic range performance as needed.

Inventive Principle:
Principle #15Dynamics

2Object-affected harmful factors

If high-gain amplifier is used to achieve low-noise signal readout, then noise is reduced, but simple amplification cannot ensure both high sensitivity and wide dynamic range

Engineering Contradiction:
ImprovenoiseVSAvoidboth high sensitivity and wide dynamic range
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent creates a multi-functional amplifier system that can perform multiple functions: noise reduction through high-gain amplification, dynamic range extension through additional amplification stages, and adaptive signal processing. The readout circuit is designed to handle both high-sensitivity signals and wide dynamic range requirements within a single integrated system, making it universally applicable to different imaging conditions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces an intermediate amplification stage between the pixel and the final readout. This intermediate stage acts as a mediator that can provide both high gain for noise reduction and additional signal conditioning to preserve dynamic range. The intermediate amplifier serves as a bridge that reconciles the conflicting requirements of noise reduction and dynamic range maintenance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8553112B2A/D converter and readout circuit
Publication Date: 2013.10.08 NAT UNIV CORP SHIZUOKA UNIV
  • US8553112B2 patent drawing
  • US8553112B2 patent drawing
  • US8553112B2 patent drawing

AI summary

An A/D converter 11 performs multiple-times sampling on a first signal S1 in a first period T1 while performing multiple-times sampling on a second signal S2 in a second period T2. An A/D converter circuit 17 provides a digital signal in response to a signal from an output 15b of a gain stage 15 in the second period T2. The digital signal may have a value “1” or a value “0”. The A/D converter circuit 17 includes a circuit 18 providing a signal SA/DM corresponding to the number of times the value “1” appears. A switch 24 operates in response to a clock signal φs and is used to sample a signal from a pixel 2a. In a first capacitor circuit 27, a switch 29 and a capacitor 31 are connected to an inverting input 23a and a non-inverting output 23b, respectively. The switch 29 operates in response to a clock signal φ3 and is used for integration in the capacitor 31.