Adaptable Open Row Memory Device for Power and Performance Optimization
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Solution Overview
Problem
Conventional SDRAM and DDR SDRAM devices have a fixed row size, which leads to sub-optimal power consumption and performance due to diverse memory access patterns in multicore systems, as they can only have one row open at a time, resulting in inefficiencies in row hits and power usage.
Innovation Solution
A memory device and system that allows an adaptable number of open rows, using a memory controller with an arbiter, memory mapper, and command generator to determine and manage the number of open rows based on memory access patterns, enabling multiple rows to be open simultaneously and optimizing power and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large row size is used, then the number of row hits is increased, but power consumption increases
Solution Approach 1:
The patent implements dynamic row size adjustment where the number of open rows is not fixed but adapts based on memory access patterns. The system can configure different numbers of open rows (e.g., 1, 2, or more) depending on the workload characteristics, allowing optimization between power consumption and row hit ratio for different scenarios.
Solution Approach 2:
The invention changes the parameter of row size from a fixed value to an adaptable parameter. By allowing the number of open rows to be configured dynamically, the system can adjust this parameter to match actual memory access patterns, thereby optimizing the trade-off between power consumption and productivity.
2Use of energy by moving object
If a small row size is used, then power consumption is reduced, but performance deteriorates due to fewer row hits
Solution Approach 1:
The system dynamically adjusts the number of open rows based on detected memory access patterns. When access patterns indicate high locality, the system opens more rows to improve row hit ratio and performance. When access patterns show low locality or diverse access, the system opens fewer rows to reduce power consumption, thus adapting to different performance-power trade-off requirements.
Solution Approach 2:
The patent employs feedback mechanisms where memory access patterns are monitored and used to adjust the number of open rows. This feedback loop allows the system to learn from actual usage behavior and configure the optimal number of open rows, balancing performance and power consumption based on real-time or historical access characteristics.
3Device complexity
If a fixed row size is used, then device complexity is reduced, but adaptability to diverse memory access patterns deteriorates
Solution Approach 1:
The patent introduces dynamic configuration capability that allows the number of open rows to be adjusted based on memory access patterns. This dynamic feature enhances adaptability to different workloads and access patterns while maintaining relatively simple hardware architecture through software-controlled configuration rather than complex hardware reconfiguration.
Solution Approach 2:
The system implements a universal mechanism that can handle diverse memory access patterns through a single adaptable design. By configuring the number of open rows dynamically, the same memory device can optimize for different access patterns (sequential, random, cached, etc.) without requiring multiple specialized hardware configurations, thus achieving multi-functionality with minimal added complexity.
Data Source
AI summary
A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.