Adapter-Board Memory System for Dynamic Server Pooling
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Solution Overview
Problem
Existing memory systems face challenges with insufficient memory resources, particularly in cloud computing environments, where memory configurations often fall short and cannot be easily expanded beyond certain limits, leading to inefficiencies and increased costs.
Innovation Solution
A memory system design that utilizes external adapter boards and connecting cables to convert high-speed interconnection signals into processor internal bus signals, enabling memory resources to be accessed and used by the processor, and supports memory pooling through the CXL protocol, optimizing spatial layout and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory resources are increased on the server, then memory capacity is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges memory resources from multiple servers into a shared memory pool that can be dynamically allocated to different servers. Multiple memory modules from different physical servers are combined and managed as a unified resource, allowing efficient memory sharing without requiring each server to have dedicated memory capacity.
Solution Approach 2:
The memory pool serves multiple functions and multiple servers simultaneously. The same memory resources can be allocated to different servers based on demand, making the memory system universal rather than dedicated to a single server. This multi-functional approach increases memory utilization efficiency.
2Quantity of substance
If memory resources are increased on the server, then memory capacity is improved, but hardware cost increases
Solution Approach 1:
The patent combines memory modules from multiple servers into a shared pool, allowing the same memory resources to serve multiple purposes. This reduces the total amount of memory hardware needed compared to providing dedicated memory for each server, thereby reducing overall hardware costs.
Solution Approach 2:
The system allows memory resources to be dynamically allocated and deallocated based on server needs. When a server no longer needs memory resources, they are returned to the pool and can be reallocated to other servers, maximizing the utilization of existing memory hardware and reducing the need for additional purchases.
3Productivity
If memory resources are dynamically allocated across servers, then memory utilization efficiency is improved, but system complexity increases
Solution Approach 1:
The patent introduces a memory management system that acts as an intermediary between physical memory modules and servers. This intermediary layer handles the complexity of dynamic allocation, translation, and management, while servers interact with a simplified interface. The intermediary absorbs the system complexity rather than exposing it to users.
Solution Approach 2:
The memory management system continuously monitors memory usage across servers and dynamically adjusts allocations based on actual demand. This feedback mechanism ensures high utilization efficiency by allocating memory to where it is most needed while automatically managing the complexity of real-time adjustments.
Data Source
AI summary
A memory system includes a first motherboard, and a processor and a high-speed interconnection channel interface that are integrated on the first motherboard; a first adapter board, and a high-speed interconnection channel interface, a chip and a memory module that are integrated on the first adapter board; and at least one connecting cable; the at least one connecting cable is used to establish a physical link between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the first adapter board, and used to convert the high-speed channel interconnection signal into a processor internal dedicated bus signal transmitted by a physical link based on a peripheral component interconnect express; and the chip of the first adapter board is used to acquire the converted processor internal dedicated bus signal, and convert the processor internal dedicated bus signal into a double data rate memory signal.