Adapter Module for Scan Testing Throughput Enhancement
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Solution Overview
Problem
Low pin count device-under-test (DUT) designs are prone to aliasing errors and have less robust data compression due to limited external scan inputs and outputs, leading to underutilization of tester resources, resulting in reduced data rate and increased testing time.
Innovation Solution
An adapter module is introduced to optimize scan testing by receiving scan inputs and outputs at different clock frequencies, allowing for efficient utilization of tester resources and enabling the DUT to operate at frequencies equal to or higher than the tester, thereby enhancing test efficiency and reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a serializer-deserializer (SerDes) is included in the DUT to increase the number of external scan inputs and outputs, then the number of scan chains is increased, but tester resources (I/O ports) remain under-utilized, causing reduced tester data rate and increased testing time
Solution Approach 1:
An adapter module is introduced as an intermediary component between the tester and the DUT. The adapter module includes a plurality of input ports coupled to tester I/O ports, a plurality of output ports coupled to DUT scan input ports, and a clock generating unit. This intermediary enables frequency conversion and proper signal distribution, allowing the tester to operate at its optimal frequency while the DUT operates at its required frequency, thereby maximizing tester resource utilization and data rate while maintaining reliable data compression
2Speed
If the DUT operates at a higher clock frequency than the tester, then the DUT can process data faster, but the tester resources are under-utilized and testing time increases
Solution Approach 1:
The adapter module implements parameter changes by converting the clock frequency from the tester's operating frequency to the DUT's required operating frequency. The clock generating unit receives a first clock signal at a first frequency from the tester and provides a second clock signal at a second frequency to the DUT. This frequency transformation allows each component to operate at its optimal speed without causing resource under-utilization or increased testing time
3Reliability
If the number of external scan inputs and outputs is increased using SerDes, then aliasing errors are reduced, but the tester I/O ports are under-utilized
Solution Approach 1:
The adapter module serves as an intermediary that efficiently maps tester I/O ports to DUT scan ports. The plurality of input ports of the adapter module are coupled to M tester I/O ports, and the plurality of output ports are coupled to P scan input ports of the DUT. This intermediary structure enables full utilization of available tester I/O ports while providing sufficient scan inputs and outputs to the DUT to prevent aliasing errors, without adding unnecessary complexity to the tester
Data Source
AI summary
Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency F1 and includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F1. Adapter module is coupled to tester and configured to receive M scan inputs at F1 and, in response, provide P scan inputs at clock frequency F2 to P scan input ports, and to receive Q scan outputs at F2 from Q scan output ports and, in response, provide N scan outputs at F1 to N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.