Peripheral Adapter Parallel TLP Processing via Steering Module
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Solution Overview
Problem
Conventional computing systems and adapters are limited in handling multiple transactions per clock cycle, as they are designed to process one transaction layer packet (TLP) at a time, leading to inefficiencies in data transfer and communication with peripheral devices.
Innovation Solution
The implementation of a steering module and dual data paths within the adapter, utilizing a 'ping-pong' scheme to efficiently route and process multiple TLPs in parallel, ensuring proper ordering and validation, and dynamic buffer sizing based on traffic patterns to enhance throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional adapter processes one TLP at a time, then the system design is simple, but the processing throughput is limited
Solution Approach 1:
The adapter is divided into multiple independent processing paths (first path and second path), each capable of processing TLPs independently. This segmentation allows parallel TLP processing, increasing throughput from one TLP per clock cycle to multiple TLPs per clock cycle without requiring complete redesign of the entire adapter architecture
Solution Approach 2:
The patent introduces a temporal dimension to processing by implementing pipelining where TLPs are processed at different stages simultaneously. The first TLP is being processed while the second TLP is prepared, creating a pipeline that processes multiple TLPs through time-based parallelism rather than spatial parallelism alone
2Speed
If multiple TLPs are processed in parallel, then the processing speed increases, but the packet ordering and validation becomes more difficult
Solution Approach 1:
Validation logic is performed in advance on each TLP before it enters the processing pipeline. The steering module pre-validates TLP parameters and determines routing decisions before the actual data transfer begins, ensuring that ordering and validity are established beforehand rather than being checked during processing
Solution Approach 2:
The patent implements feedback mechanisms where the steering module receives status information about processed TLPs and uses this feedback to manage the pipeline. Validation results and processing status are fed back to control the steering decisions for subsequent TLPs, ensuring proper ordering and detecting errors in parallel processing
3Productivity
If fixed buffer sizes are used, then the device complexity is low, but the buffer efficiency under varying traffic patterns decreases
Solution Approach 1:
The buffer size is made dynamic rather than fixed, allowing it to adjust based on actual traffic patterns. The system can expand or shrink buffer allocation according to the volume and characteristics of incoming TLPs, optimizing buffer utilization efficiency without requiring overly complex buffer management hardware
Solution Approach 2:
The patent changes the buffer parameter from a static value to a variable that can be adjusted based on traffic conditions. By monitoring traffic patterns and adapting buffer size accordingly, the system achieves higher buffer efficiency while maintaining manageable complexity through parameter-based adaptation rather than structural complexity
Data Source
AI summary
Methods and device coupled to a computing device and a network device are provided. A first module receives a first packet and a second packet via a same single data path from the computing device. A second module receives the first packet at a first buffer via a first path and the second packet at a second buffer via a second path. The first module uses a steering mechanism to steer the first packet in the first path and the second packet in the second path. The second module uses an arbitration module to select the first packet and the second packet for maintaining an order in which the first packet and the second packet are received and for sending the first packet and the second packet to a third module for further processing.