Array Substrate Adapting Via Structure for Higher Aperture Ratio
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Solution Overview
Problem
Display panels in the IADS mode suffer from small aperture ratio and low yield due to the dual-hole structure, which requires a larger space and affects the pixel electrode area and orientation film uniformity, leading to display defects like panel stains.
Innovation Solution
An array substrate design with a single transferring through hole that connects the pixel electrode and drain electrode, accompanied by compensation blocks to ensure reliable connection and reduce the number of through holes, maintaining a high aperture ratio and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional via hole structures are used to connect pixel electrodes and transistor electrodes, then electrical connection is achieved, but the number of via holes increases and aperture ratio decreases
Solution Approach 1:
The patent merges multiple via holes into a single adapting via hole that simultaneously connects the pixel electrode to both the drain electrode and source electrode. This consolidation reduces the total number of via holes required and increases the aperture ratio while maintaining all necessary electrical connections for the thin-film transistor operation.
Solution Approach 2:
The adapting via hole serves multiple functions simultaneously: it provides electrical connection between the pixel electrode and the drain electrode, and between the pixel electrode and the source electrode. This multi-functional via hole structure eliminates the need for separate via holes for each connection, thereby reducing via hole count and increasing aperture ratio.
2Reliability
If multiple via holes are used for connecting pixel electrode to drain and source electrodes, then electrical connections are established, but manufacturing complexity and yield issues arise
Solution Approach 1:
By combining multiple connection functions into a single adapting via hole, the manufacturing process is simplified. Instead of requiring precise alignment and formation of multiple separate via holes, the process now requires only one via hole formation step, reducing manufacturing complexity and improving product quality and yield.
Solution Approach 2:
The patent performs preliminary planning of the via hole structure during the design phase, where the adapting via hole is strategically positioned and dimensioned to accommodate multiple electrical connections. This preliminary action ensures that subsequent manufacturing steps are simplified and that product quality is improved by reducing the number of critical alignment steps required.
Data Source
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AI summary
Disclosed are an array substrate and a method for preparing same, and a display panel. The array substrate comprises: a base (10); a pixel electrode (50) and a thin-film transistor which are provided on the base (10); a passivation layer (16) covering the thin-film transistor and the pixel electrode (50), wherein an adapting via hole (K1, K2), which simultaneously exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin-film transistor, is provided in the passivation layer (16); and a connection electrode (60) which is provided on the passivation layer (16) and is at the adapting via hole (K1, K2), wherein the connection electrode (60) is simultaneously connected, through the adapting via hole (K1, K2), to the pixel electrode (50) and the drain electrode (15) or the source electrode (14). Realizing connection between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) by providing the adapting via hole (K1, K2) effectively reduces the number of via holes, increases an aperture ratio of the display panel, improves product quality, and improves the yield.