Adaptive ADC Bit Adjustment for Small-Signal Precision
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Solution Overview
Problem
Existing ADC circuits require higher bit precision for larger dynamic range signals, leading to increased chip size, which is inefficient and costly.
Innovation Solution
Implement a method involving multiple ADC conversions and adjusting the least significant bit based on higher bits' values to enhance precision without increasing circuit size, using a conversion and control module to manage these processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-precision ADC with higher bit digital signal is used to output signals of large dynamic range, then the ADC precision is improved, but the ADC circuit size needs to be doubled for each additional bit
Solution Approach 1:
The patent divides the ADC conversion process into multiple stages: a first ADC performs initial conversion, and a second ADC performs subsequent conversion only when the first ADC's output indicates small signal values (all higher bits are 0). This segmentation allows the system to achieve high precision for small signals without requiring a single high-bit ADC that would consume excessive area.
Solution Approach 2:
The patent dynamically adjusts the ADC circuit configuration based on the input signal characteristics. The control module monitors the output of the first ADC and dynamically determines whether to engage the second ADC for additional conversion, thereby adapting the precision level to the actual signal requirements rather than maintaining fixed high precision for all signals.
2Measurement precision
If multiple ADC conversions are performed to improve precision for small signals, then the ADC precision is improved, but the conversion time increases
Solution Approach 1:
The patent implements dynamic conversion time adjustment by using a control module that monitors the first ADC's output. When the output indicates a large signal (any higher bit is 1), the conversion process terminates after the first ADC, maintaining fast response. When the output indicates a small signal (all higher bits are 0), the second ADC is engaged for additional conversion, accepting the time penalty only when necessary for precision.
Solution Approach 2:
The patent employs periodic monitoring of the first ADC output bits to determine whether additional conversion is needed. The control module periodically checks the higher bits of the first ADC output and triggers the second ADC conversion only during periods when small signals are detected, rather than performing multiple conversions for every input signal.
Data Source
AI summary
Provided is an ADC circuit based signal digitalization method, including: inputting the analog signal to the ADC circuit, and after being converted by the ADC circuit for the first time, outputting a first ADC output value Mi; adjusting the least significant bit of the ADC circuit based on the value of the higher bits of the output value Mi, turning down the least significant bit of the ADC circuit, when all the values of the higher bits of the output value Mi are 0; inputting the analog signal to the ADC circuit again, and then outputting the ADC output value Mi+1 for the i+1 time; outputting the final signal conversion result and the adjusted least significant bit based on all the ADC output values. The present invention could improve the ADC precision of small signals without increasing the ADC circuit size.