Adaptive ADC Clock Delay for Accurate Undersampling
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Solution Overview
Problem
Current analog-to-digital converters face challenges in performing accurate undersampling and analog-to-digital conversion when the sampling rate changes, particularly in wireless communication systems that require compatibility with various bands and wide bandwidths, as a constant delay time in the delay circuit can lead to inadequate conversion.
Innovation Solution
An analog-to-digital converter system that includes a sample-and-hold circuit, a delay circuit, an analog-to-digital converter circuit, and a delay adjustment circuit, which adjusts the delay time of the sampling clock signal based on changes in frequency to ensure stable sampling and holding periods, allowing for effective undersampling and digital signal conversion across varying sampling rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant delay time is used in the delay circuit, then the device complexity is reduced, but the conversion accuracy deteriorates when sampling rate changes
Solution Approach 1:
The delay circuit is designed with variable delay time that can be dynamically adjusted according to the sampling rate. The delay adjustment circuit receives the sampling clock signal and adjusts the delay time of the sampling clock signal to be input to the ADC circuit, ensuring that the sampling timing remains accurate even when the sampling rate changes. This dynamic adjustment resolves the contradiction by making the delay circuit adaptive rather than fixed.
Solution Approach 2:
The delay time parameter in the delay circuit is changed based on the sampling rate. When the sampling rate changes, the delay adjustment circuit modifies the delay time parameter to maintain proper synchronization between the sample-and-hold circuit and the ADC circuit. This parameter change approach allows the system to maintain conversion accuracy across different operating conditions.
2Adaptability or versatility
If the sampling rate is changed to support various bands and bandwidths, then the adaptability is improved, but the conversion accuracy deteriorates due to inadequate sampling
Solution Approach 1:
The system dynamically adjusts the delay time in the delay circuit according to the sampling rate being used. This allows the analog-to-digital converter to maintain accurate sampling and conversion across different sampling rates required for various bands and bandwidths, resolving the contradiction between adaptability and conversion accuracy.
Solution Approach 2:
The delay adjustment circuit receives feedback about the sampling rate and automatically adjusts the delay time accordingly. This feedback mechanism ensures that the sampling timing remains synchronized and accurate regardless of which sampling rate is currently being used, maintaining conversion accuracy across all supported bands and bandwidths.
Data Source
AI summary
An analog-to-digital converter (1) includes an S/H circuit (10) configured to sample and hold an analog input signal (IN) in synchronization with a sampling clock signal (CLK), a delay circuit (20) configured to delay the sampling clock signal (CLK), an ADC circuit (30) configured to sample an output signal (S/H_out) of the S/H circuit (10) in synchronization with the sampling clock signal (CLK_delay) that is delayed, and output a digital signal (OUT) corresponding to an amplitude of the output signal that is sampled, and a delay adjustment circuit (40) configured to adjust a delay time of the sampling clock signal (CLK) in the delay circuit (20) in accordance with a change in frequency of the sampling clock signal (CLK).