Adaptive ADC Dithering for Higher SFDR Without SNR Loss
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face limitations in achieving high linearity due to nonlinearities in sampling and quantization, with calibration and dithering methods being complex, requiring high accuracy, and affecting signal-to-noise ratio (SNR) and power dissipation.
Innovation Solution
An ADC circuit with a sample-and-hold amplifier (SHA) that adds a dither signal adjusted to prevent the output from exceeding the ADC's input voltage range, allowing high-amplitude dithering without reducing the input signal amplitude, thus optimizing signal-to-noise ratio and spurious-free dynamic range (SFDR) without the drawbacks of conventional dithering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dither signal is added to improve linearity and SFDR, then SFDR is improved, but the total power converted by the ADC increases requiring reduced input signal amplitude which reduces SNR
Solution Approach 1:
The patent applies dynamics by making the dither signal adaptive rather than static. The dither signal amplitude and characteristics are dynamically adjusted based on the input signal characteristics and ADC operating conditions. This allows the system to optimize SFDR improvement while minimizing the negative impact on SNR by reducing dither amplitude when input signals are strong and increasing it when input signals are weak.
Solution Approach 2:
The patent changes parameters of the dither signal including amplitude, frequency, and spectral characteristics to optimize performance. By varying these parameters dynamically, the system can improve SFDR without permanently reducing input signal amplitude, thus maintaining better SNR compared to conventional dithering approaches.
2Measurement precision
If calibration is performed to correct quantization errors, then linearity is improved, but the ADC must be disconnected from signal path causing operational interruption and complexity increases
Solution Approach 1:
The patent ensures continuous operation by applying dithering during normal ADC operation rather than requiring separate calibration phases. The dither signal is added continuously to the input signal path, allowing linearity improvement without disconnecting the ADC from the signal path, thus maintaining operational continuity and eliminating interruptions.
Solution Approach 2:
The dithering approach enables the ADC to self-correct linearity issues during normal operation without requiring external calibration equipment or procedures. The system continuously applies dither and processes signals through the quantizer, allowing real-time linearity improvement without operational interruption.
3Measurement precision
If dither signal amplitude is increased to improve SFDR, then SFDR improvement increases, but power dissipation increases and input signal amplitude must be reduced
Solution Approach 1:
The patent dynamically adjusts dither signal amplitude based on input signal characteristics and desired performance levels rather than using a fixed high amplitude. This allows the system to achieve adequate SFDR improvement with lower average power dissipation by adapting dither amplitude to actual operating conditions.
Solution Approach 2:
The patent optimizes dither signal parameters including amplitude, frequency spectrum, and temporal characteristics to achieve maximum SFDR improvement per unit of power consumed. By carefully selecting and dynamically adjusting these parameters, the system achieves efficient power utilization while maintaining SFDR performance.
Data Source
AI summary
A dynamic dithering method is provided for improving linearity in analog-to-digital converters.