Adaptive ADC Sampling Control for Lower Waveform Storage
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Solution Overview
Problem
Existing AD conversion devices face challenges in reducing storage capacity due to the inclusion of time stamps in waveform data, leading to increased memory requirements when handling high-frequency signals.
Innovation Solution
An AD conversion device that includes a decimation controller to identify high-frequency components in analog signals, setting regions for high-speed and decimation sampling, and uses a write-enable signal and decimation bit information to store sampling data at reduced rates, associating data with count values from a counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency is increased to capture high-frequency signals, then the measurement precision is improved, but the storage capacity requirement increases
Solution Approach 1:
The patent segments the sampling data into two categories: normal sampling data and abnormal sampling data (containing high-frequency components). By separating these data types, the system can apply different storage strategies - decimation for normal data and full-resolution storage for abnormal data - thereby reducing overall storage requirements while maintaining measurement precision for critical signals.
Solution Approach 2:
The patent applies local quality by using decimation (reducing sampling rate) only for portions of the signal where high-frequency components are absent, while maintaining full sampling resolution for segments containing abnormal signals. This localized application of different quality levels optimizes storage efficiency without sacrificing measurement accuracy where needed.
2Reliability
If all sampling data is stored in the storage unit, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent changes the storage parameter dynamically based on signal characteristics. By monitoring for high-frequency components and adjusting the sampling rate parameter accordingly (full rate for abnormal data, decimated rate for normal data), the system maintains data reliability while simplifying the storage system's requirements and reducing peripheral circuit complexity.
3Quantity of substance
If the sampling rate is reduced to decrease storage requirements, then the loss of substance is reduced, but the measurement precision deteriorates
Solution Approach 1:
The patent implements dynamic sampling rate adjustment based on real-time signal analysis. The system continuously monitors for high-frequency components and adapts the sampling rate accordingly - using full sampling rate when abnormal signals are detected and reduced rate when signals are normal. This dynamic approach prevents loss of measurement precision while achieving storage reduction.
Solution Approach 2:
The patent employs feedback by using the detected high-frequency components as a control signal to adjust the sampling rate. The detection unit identifies abnormal signals and feeds this information back to the storage control mechanism, which then adjusts the sampling strategy to maintain precision for critical events while reducing storage for routine operation.
Data Source
AI summary
An AD conversion device includes an AD converter that outputs an analog signal as sampling data for every sampling point based on a sampling frequency, a controller, and a storage circuit, the controller includes a buffer memory which temporarily stores the sampling data from the AD converter in time series and from which the sampling data is read out in time series, and a decimation controller, the decimation controller outputs a write-enable signal indicating write-enabled for the selected sampling data in the decimation region and the sampling data in the high-speed sampling region, and outputs decimation bit information indicating whether the sampling data is the sampling data of the decimation region or the sampling data of the high-speed sampling region, and the storage circuit stores the sampling data stored in the buffer memory in association with the decimation bit information, in response to the write-enable signal.