Adaptive Aggregation Memory Buffer for Resistive Memory Endurance

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Solution Overview

Problem

Emerging memory technologies like resistive RAM and FeRAM face challenges in power consumption and endurance, limiting their adoption in portable devices and datacenters due to higher power dissipation and lower endurance compared to traditional SRAM and DRAM, necessitating innovative solutions for improved performance and efficiency.

Innovation Solution

The integration of an adaptive aggregation memory buffer and an integrated processor within the memory array, which aggregates localized memory requests and optimizes memory settings to enhance endurance, performance, and power consumption by reducing write and read cycles, and employing programmable memory management to balance energy efficiency with performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If emerging memory technologies (resistive RAM, FeRAM) are used to achieve non-volatile high-density storage, then memory density and non-volatility are improved, but power consumption increases and endurance decreases

Engineering Contradiction:

Improvememory densityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory system is divided into multiple banks, with each bank containing sense amplifiers and write buffers that can operate independently. This segmentation allows parallel processing of memory operations across different banks, improving overall throughput and reducing the power consumption per operation by distributing the workload across multiple smaller units rather than one large unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Write buffers are used to pre-process and queue write operations before they are committed to the memory array. This preliminary action allows write operations to be aggregated and optimized, reducing the total number of write cycles needed and thereby improving endurance while maintaining acceptable power consumption levels.

Inventive Principle:

Principle #10Preliminary action

2Quantity of substance

If emerging memory technologies (resistive RAM, FeRAM) are used to achieve non-volatile high-density storage, then memory density and non-volatility are improved, but endurance decreases

Engineering Contradiction:

Improvememory densityVSAvoidendurance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The memory array is divided into multiple banks that can be independently managed. This segmentation allows wear to be distributed across multiple banks rather than concentrated in a single array, effectively increasing the overall endurance of the memory system by rotating usage across banks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Write buffers pre-process and aggregate write operations before committing them to the memory array. This preliminary action reduces the total number of write cycles by combining multiple small writes into fewer larger writes, thereby reducing wear on the memory cells and improving endurance.

Inventive Principle:

Principle #10Preliminary action

3Speed

If traditional SRAM and DRAM are used to achieve fast read and write times, then access speed is improved, but volatility increases and refresh requirements reduce endurance

Engineering Contradiction:

Improveaccess speedVSAvoidendurance

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The memory system is designed to provide multiple functions within a unified architecture, combining the fast access characteristics of volatile memory with the non-volatility and high endurance of emerging memory technologies. The system can operate in different modes (volatile mode, non-volatile mode, hybrid mode) depending on the application requirements, achieving both speed and endurance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Quantity of substance

If external memory is used to compensate for lack of on-chip memory density scaling, then memory capacity is improved, but access power consumption increases significantly

Engineering Contradiction:

Improvememory capacityVSAvoidaccess power consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The invention merges multiple memory technologies (volatile and non-volatile, high-speed and high-density) into a unified on-chip memory system. This integration eliminates the need for external memory connections, reducing access power consumption by 30-60× compared to external memory while maintaining high capacity through the combined memory banks.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20240420761A1Endurance, power, and performance improvement logic for a memory array

Publication Date: 2024.12.19 NVMENGINES INC

AI summary

Logic to provide improved endurance, performance, and power optimizing capabilities for a resistive memory, ferro-electric RAM (FeRAM) memory, or embedded flash memory is disclosed herein. In one embodiment, a memory subsystem comprises a resistive memory array; an adaptive aggregation memory buffer that has configurable settings for optimizing endurance, power, or performance of the memory subsystem; an endurance management and control logic (EMCL) coupled to the adaptive aggregation memory buffer; and an integrated processor coupled to the EMCL. At least one of the integrated processor and EMCL is configured to determine whether memory requests to a particular memory region during a time window can be aggregated into an aggregate memory request and to optimize memory settings, and to cause the aggregate memory request and memory settings to be sent to the resistive memory array, FeRAM memory, or embedded flash memory to optimize parameters including memory performance and memory endurance.