Adaptive Analog Partial Sum Accumulation for Low-ADC CiM
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Solution Overview
Problem
Conventional analog-based Compute-in-Memory (CiM) solutions face limitations in energy efficiency due to high power consumption from Analog to Digital Conversion (ADC) hardware, which is exacerbated by a tradeoff between MAC energy efficiency and ADC digitization accuracy, where increasing the number of multiplication products in a partial sum for analog accumulation either reduces energy efficiency or increases ADC energy consumption.
Innovation Solution
An adaptive analog partial sum accumulation scheme is introduced, which includes an additional accumulation stage between the analog output activation lines and the ADC input, utilizing an overflow detector to control the accumulation process, thereby increasing the number of multiplication products before digitization without increasing the averaging factor, thus reducing ADC energy consumption and preventing saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of multiplication products in a partial sum for analog accumulation is increased to reduce ADC energy consumption, then ADC energy consumption per MAC operation decreases, but the averaging factor increases which constrains ADC digitization precision and may cause saturation
Solution Approach 1:
The patent divides the accumulation process into multiple stages: first accumulating multiplication products in the analog domain to form partial sums, then using a second analog accumulation stage to accumulate multiple partial sums before ADC conversion. This segmentation allows more multiplication products to be processed before digitization without increasing the averaging factor for individual MAC operations, thereby reducing ADC energy consumption while maintaining precision.
Solution Approach 2:
The patent adds an additional dimension to the accumulation process by introducing a second analog accumulation stage that operates in parallel with the first stage. This enables the system to accumulate multiplication products across multiple dimensions (multiple partial sums) before ADC conversion, effectively increasing the number of products processed without compromising the precision requirements of individual conversions.
2Productivity
If more multiplication products are summed in the analog domain for a single ADC digitization to amortize ADC energy consumption, then energy efficiency improves, but the larger averaging factor constrains ADC accuracy requirements and increases bit requirements
Solution Approach 1:
The patent segments the accumulation of multiplication products into multiple analog stages. The first stage accumulates products within a MAC operation to form a partial sum, while the second stage accumulates multiple partial sums from different MAC operations. This segmentation allows the system to process more total products before ADC conversion without increasing the averaging factor for any single conversion, thereby maintaining ADC precision requirements while improving energy efficiency.
Solution Approach 2:
The patent maintains continuous useful action by keeping the analog accumulation process running across multiple MAC operations without interrupting for ADC conversion. The second analog accumulation stage continuously accumulates partial sums from multiple MAC operations, allowing the system to amortize ADC energy consumption over many operations while maintaining continuous computation flow and avoiding idle periods.
3Device complexity
If analog partial sum accumulation is performed without additional stages, then device complexity remains low, but ADC energy consumption per MAC operation is high due to frequent digitization
Solution Approach 1:
The patent merges multiple accumulation functions into a unified analog accumulation architecture. The first analog accumulation stage handles multiplication product summation within MAC operations, while the second stage accumulates partial sums across operations. Both stages operate in the analog domain and are merged into a single integrated system that shares resources, thereby reducing overall device complexity compared to having separate digital accumulation stages while significantly reducing ADC energy consumption.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.