Memory Read Error Correction With Adaptive BCH Bit Flipping
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Solution Overview
Problem
Memory systems face complexity and performance deterioration issues due to repetitive error correction operations, which affect the efficiency and stability of data processing in portable electronic devices.
Innovation Solution
A memory system and operating method that perform bit flipping operations during repetitive error correction using the BCH decoding scheme, varying the number of flip bits for constituent codes, and gradually increasing the number of flip bits in the least reliable code until successful correction, while holding or adjusting flip bits in other codes based on error correction outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repetitive error correction operations are performed using traditional decoding schemes, then error correction capability is improved, but decoding latency increases and performance deteriorates
Solution Approach 1:
The patent applies dynamics by making the bit flipping operation adaptive rather than static. The controller dynamically adjusts the number of bit flipping operations based on the reliability status of each constituent code, performing more flips on less reliable codes and fewer or no flips on more reliable codes. This dynamic adaptation resolves the contradiction by optimizing error correction effort where needed while avoiding unnecessary operations elsewhere, thereby reducing overall decoding latency while maintaining error correction capability.
Solution Approach 2:
The patent changes the parameter of bit flipping count from a fixed value to a variable that depends on code reliability. By monitoring the reliability status of each constituent code and adjusting the number of bit flipping operations accordingly, the system achieves better error correction performance on unreliable codes while minimizing operations on reliable codes. This parameter change resolves the contradiction between thorough error correction and reduced decoding latency.
2Reliability
If traditional error correction methods are used, then error handling is improved, but system complexity increases
Solution Approach 1:
The patent applies local quality by treating different constituent codes differently based on their individual reliability characteristics. Rather than applying a uniform error correction approach to all codes, the system identifies least reliable constituent codes and applies bit flipping operations selectively to those specific codes. This localized approach improves error handling where needed while avoiding unnecessary complexity in processing reliable codes, thus resolving the contradiction between error handling capability and system complexity.
Solution Approach 2:
The patent segments the error correction process by dividing constituent codes into different reliability groups. The controller identifies and separates least reliable constituent codes from more reliable ones, applying different bit flipping strategies to each segment. This segmentation allows the system to focus computational resources on problematic areas while simplifying processing for reliable segments, thereby reducing overall system complexity while maintaining robust error handling.
3Ease of operation
If fixed number of bit flipping operations is performed in each loop, then processing simplicity is improved, but error correction effectiveness deteriorates
Solution Approach 1:
The patent transforms the static bit flipping count into a dynamic parameter that adapts to code reliability. Instead of performing a fixed number of bit flipping operations on all codes, the system adjusts the flipping count based on each code's reliability status. This dynamic approach maintains processing simplicity through automated reliability assessment while dramatically improving error correction effectiveness by concentrating flips where they are most needed.
Solution Approach 2:
The patent implements feedback by using reliability status information from decoding results to guide subsequent bit flipping operations. The controller monitors the performance of each constituent code and uses this feedback to adjust the number of bit flipping operations in subsequent loops. This feedback mechanism ensures that error correction effectiveness is improved without significantly complicating the processing, as the adjustments are based on clear reliability metrics.
Data Source
AI summary
A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.