Adaptive Source-Line Bias Decoder for Precise NVM Synapse Tuning
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability, as CMOS-implemented synapses are too bulky for the high number of neurons and synapses required.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, which allow for continuous and precise tuning of memory states, enabling efficient vector-matrix multiplication and reducing the need for separate multiplication and addition logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS analog circuits are used for artificial neural networks, then the neural network can be implemented with standard semiconductor technology, but the synapses become too bulky to achieve the high number of neurons and synapses required for high-performance processing
Solution Approach 1:
The patent merges the memory function and computation function into a single integrated structure by using non-volatile memory cells (such as flash memory cells with floating gates) to store synaptic weights. This eliminates the need for separate multiplication and addition logic circuits, thereby reducing the area per synapse while maintaining manufacturability with standard semiconductor processes.
Solution Approach 2:
The non-volatile memory cell serves multiple functions: it stores the synaptic weight value, performs analog multiplication of input signals, and maintains the weight state persistently without requiring additional circuitry. This multi-functionality reduces the overall synapse area while keeping the manufacturing process compatible with existing CMOS technology.
2Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then the required computational parallelism can be achieved, but the energy efficiency becomes mediocre compared to biological networks
Solution Approach 1:
The patent replaces the mechanical/digital computation system with an analog electrical system. Non-volatile memory cells perform analog multiplication and addition operations directly in the analog domain, eliminating the need for digital signal processing and associated overhead. This analog computation approach achieves high computational parallelism with significantly improved energy efficiency, mimicking the energy-efficient processing of biological neural networks.
3Device complexity
If non-volatile memory arrays are used as synapses, then energy efficiency and hardware complexity are reduced, but precise tuning of memory states and stable bias voltages are required for accurate computation
Solution Approach 1:
The patent implements feedback mechanisms including sense amplifiers that read the analog output currents from the memory array and convert them to voltage signals. Digital-to-analog converters (DACs) adjust control gate biases based on feedback from the computed results, enabling precise tuning of memory states and compensation for process variations. This feedback system ensures accurate computation while maintaining the simplicity of using non-volatile memory arrays as synapses.
Solution Approach 2:
The patent utilizes adjustable bias voltages applied to control gates of the non-volatile memory cells to dynamically tune the operating point and sensitivity of each synapse. By changing the gate bias parameters, the system can optimize the precision of weight storage and computation, allowing precise memory state tuning without increasing hardware complexity.
Data Source
AI summary
In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.