Adaptive Bias Decoder for Source-Line-Aware Erase Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of high computational parallelism and energy efficiency, with CMOS-implemented synapses being too bulky for the required number of neurons and synapses.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, where each memory cell stores weight values on a floating gate, allowing for continuous programming and reading without disturbing other cells, and implementing a vector-matrix multiplier array for efficient in-situ computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS analog circuits are used to implement synapses, then the neural network can perform computation, but the synapse circuits become too bulky for the required number of neurons and synapses
Solution Approach 1:
The patent merges memory and computation functions into a single non-volatile memory array structure. Memory cells store synapse weights while simultaneously performing analog multiplication and addition operations, eliminating the need for separate CMOS logic circuits for each synapse. This consolidation dramatically reduces the area required per synapse while maintaining full computational capability.
Solution Approach 2:
The non-volatile memory array serves multiple functions: it stores synapse weights, performs analog multiplication of inputs by weights, sums the results, and retains the computed values. This multi-functionality eliminates the need for dedicated CMOS circuits for each operation, reducing overall circuit area while preserving computational productivity.
2Productivity
If digital supercomputers or GPU clusters are used to achieve high connectivity and computational parallelism, then the neural network complexity can be achieved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital CMOS-based computational mechanics with analog electrical field-based computation in non-volatile memory cells. Analog voltages and currents naturally perform multiplication and addition through Ohm's law and Kirchhoff's current law, eliminating the need for energy-intensive digital logic operations and data movement between memory and processing units.
Solution Approach 2:
The non-volatile memory array performs computation using the same physical structure that stores data, without requiring separate processing units or data transfer mechanisms. The memory cells themselves execute the neural network operations by naturally responding to applied voltages with proportional currents, achieving high parallelism with minimal energy consumption.
3Productivity
If non-volatile memory arrays are used as synapses, then in-situ computation can be performed, but precise control of source line voltage is required to prevent disturbances to unselected cells
Solution Approach 1:
The patent implements dynamic voltage control of the source line, adjusting its potential during different phases of the read operation. The source line voltage transitions between different levels (e.g., 0V, Vread, and intermediate values) to selectively enable or disable current flow through specific memory cells. This dynamic adjustment allows precise control of which cells contribute to the output sum without requiring complex per-cell control circuits.
Solution Approach 2:
The system uses feedback mechanisms to monitor and adjust the source line voltage based on the operational state and measured currents. By sensing the current flowing through selected and unselected cells and adjusting the source line potential accordingly, the system prevents unwanted voltage drops or disturbances that could affect unselected cells, ensuring accurate read operations.
Data Source
AI summary
In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.