Adaptive-Bias Transconductor Circuit for Continuous-Time ADC Input
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Solution Overview
Problem
Existing sensor devices, such as MEMS microphones, require a voltage buffer or voltage gain stage due to discrete time switched capacitors, which can be inefficient when converting analog output signals to digital signals, and there is a need for a transconductor circuitry with adaptive biasing to interface with continuous time analog-to-digital converters.
Innovation Solution
A transconductor circuitry with adaptive biasing that converts voltage signals from sensors into differential currents, utilizing controllable current sources and a control circuit to adjust biasing currents based on sensing signals, and includes resistive elements for degeneration and a reference generator to mitigate common mode voltage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete time switched capacitor ADC is used, then the ADC can convert analog output signals to digital signals, but the system requires a voltage buffer or voltage gain stage which increases device complexity and reduces efficiency
Solution Approach 1:
The patent extracts the voltage-to-current conversion function from the traditional voltage buffer/gain stage architecture and integrates it directly into the ADC input interface through transconductor circuitry. This eliminates the separate voltage buffer stage while maintaining the necessary signal conversion capability, thereby reducing device complexity without sacrificing reliability
Solution Approach 2:
The patent merges the transconductor function with the ADC input stage, combining voltage-to-current conversion and signal conditioning into a single integrated circuit block. This consolidation eliminates the need for separate voltage buffer stages and reduces the overall number of components while maintaining full functionality
2Adaptability or versatility
If transconductor circuitry is used to convert voltage output signal to differential current for continuous time ADC, then the ADC can operate with continuous time topology, but the transconductor requires adaptive biasing control which increases device complexity
Solution Approach 1:
The patent implements feedback control where the biasing current of the transconductor is automatically adjusted based on the differential input signal level. The control circuit monitors the signal amplitude and dynamically modifies the biasing current to maintain optimal transconductance, enabling continuous time ADC operation without requiring complex manual biasing arrangements
Solution Approach 2:
The patent introduces dynamic biasing control where the transconductor's operating point is continuously adapted according to the input signal characteristics. This dynamic adjustment allows the circuit to maintain optimal performance across varying signal levels while interfacing with continuous time ADC, transforming a static biasing problem into a dynamically optimized system
3Ease of manufacture
If fixed biasing current is applied to transistors, then the circuit is simple to implement, but the transconductor shows high noise and signal distortion at varying input signal levels
Solution Approach 1:
The patent changes the biasing current parameter dynamically based on the input signal level rather than using a fixed value. The control circuit adjusts the biasing current to match the signal amplitude, maintaining optimal transconductance and minimizing noise and distortion across the full dynamic range of input signals while keeping the implementation relatively simple
Data Source
AI summary
A transconductor circuitry (10) with adaptive biasing comprises a first input terminal (E10a) to apply a first input signal (inp), and a second input terminal (E10b) to apply a second input signal (inn). A control circuit (200) is configured to control a first controllable current source (110) in a first current path (101) and a second controllable current source (120) in a second current path (102) in response to at least one of a first potential of a first node (N1) of the first current path (101) and a second potential of a second node (N2) of the second current path (102). The first node (N1) is located between a first transistor (150) and the first controllable current source (110), and the second node (N2) is located between a second transistor (160) and the second controllable current source (120).