Adaptive Bias Transconductor for Low-Noise Sub-Sampling PLLs
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Solution Overview
Problem
Phase-locked loops (PLLs) in semiconductor devices face challenges such as increased power consumption, noise, and non-linearities due to feedback divider scaling and charge pump mismatches, which affect jitter and spur generation, limiting their gain and noise performance.
Innovation Solution
A sub-sampling phase lock loop (SSPLL) with a transconductor circuit and an adaptive bias circuit is employed, which generates a tuning signal to adjust the voltage-controlled oscillator (VCO) and cancels offset signals using a nulling signal, reducing power consumption and noise through adaptive bias offset cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If feedback divider ratio is increased to support higher VCO frequencies, then frequency range is improved, but power consumption increases and noise increases
Solution Approach 1:
The patent extracts the feedback divider from the signal path by using a sub-sampling architecture where the VCO output is directly sampled by a phase detector without passing through a feedback divider. This eliminates the feedback divider's power consumption and noise contribution while maintaining frequency locking capability through the sub-sampling phase detector that compares the VCO output directly with a reference signal at a lower frequency.
Solution Approach 2:
The patent uses a replica charge pump circuit that copies the structure and biasing of the main charge pump to generate offset cancellation signals. The replica circuit replicates the mismatch characteristics without affecting the main signal path, allowing offset correction to be applied separately while maintaining the original charge pump's performance.
2Power
If charge pump biasing current is increased to increase gain, then gain is improved, but power consumption increases and device size increases
Solution Approach 1:
The patent implements dynamic biasing where the charge pump operates with variable biasing conditions. The offset cancellation circuit dynamically adjusts the charge pump's operating point by applying nulling signals that effectively increase the signal gain without requiring proportional increases in bias current. This allows the charge pump to maintain high gain at lower power consumption levels by optimizing its operating conditions in real-time.
Solution Approach 2:
The patent introduces an intermediary offset cancellation circuit that mediates between the charge pump and the loop filter. This circuit generates nulling signals that compensate for charge pump mismatches and non-linearities, effectively enhancing the charge pump's gain and linearity without requiring increased bias current or device size. The intermediary circuit processes the charge pump output and corrects its deficiencies before passing the signal to the loop filter.
3Adaptability or versatility
If charge pump devices are scaled up to support higher VCO control voltage range, then voltage range is improved, but power consumption increases
Solution Approach 1:
The patent uses dynamic offset cancellation to adapt the charge pump's effective output range without scaling up the physical devices. The nulling signals dynamically adjust the charge pump's transfer characteristic to extend its effective voltage range while maintaining the same device dimensions and power consumption. This allows the charge pump to achieve higher adaptability through signal processing rather than hardware scaling.
4Stability of the object's composition
If PFD and charge pump are linearized by offsetting charge pump to only source current, then linearity is improved, but noise increases and reference spur increases
Solution Approach 1:
The patent implements feedback-based offset cancellation where the nulling signals are generated by sampling the charge pump's own output and comparing it with the expected linear response. The error signal is fed back to adjust the charge pump's operation in real-time, correcting non-linearities while maintaining balanced source and sink currents. This feedback mechanism preserves current balance to minimize noise and reference spurs while achieving linearity through continuous correction rather than asymmetric biasing.
Data Source
AI summary
Semiconductor devices for synchronizing networks are described. The semiconductor device includes a timing circuit having a sub-sampling phase lock loop. The sub-sampling phase lock loop includes a radio frequency sampler circuit that is configured to generate at least one error signal corresponding to a phase difference between an output signal of a voltage-controlled oscillator and a reference signal and a transconductor circuit that is configured to generate a tuning signal based on the at least one error signal. The tuning signal is configured to tune the voltage-controlled oscillator. The sub-sampling phase lock loop further includes an adaptive bias circuit that is configured to generate a nulling signal based on an offset in the tuning signal created by the transconductor circuit and provide the nulling signal to the transconductor circuit. The transconductor circuit is configured to adjust the tuning signal based on the nulling signal.