Adaptive BMC Duty Cycle Circuit for Reliable USB PD Decoding
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Solution Overview
Problem
USB interfaces face challenges in providing sufficient power to high-power devices due to limitations in power supply capacity, and Bi-phase Mark Coding (BMC) signals are prone to distortion from frequency deviations, direct-current biases, and level conversion inconsistencies, leading to decoding failures.
Innovation Solution
A signal duty cycle adaptive-adjustment circuit and method that includes an analog level comparison circuit, path switches, a decoding circuit, parameter extraction and estimation circuit, error generation circuit, filter feedback circuit, and digital-to-analog conversion circuit, which adjusts the duty cycle of received BMC signals to ensure proper decoding by eliminating distortions caused by direct-current biases and inconsistent voltage conversion rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If Bi-phase Mark Coding (BMC) is used for USB PD communication, then the communication simplicity and flexibility are improved, but the signal is prone to distortion from frequency deviations and direct-current biases, leading to decoding failures
Solution Approach 1:
The patent applies preliminary action by performing duty cycle adjustment before decoding. The adjustment circuit pre-processes the BMC signal to correct duty cycle distortion caused by frequency deviations and direct-current biases, ensuring the signal is properly conditioned before it reaches the decoding stage, thereby preventing decoding failures
Solution Approach 2:
The patent implements feedback by continuously monitoring the duty cycle of the received BMC signal and dynamically adjusting the adjustment amount. The circuit calculates the difference between the actual duty cycle and the target duty cycle, then uses this feedback to fine-tune the signal adjustment, improving decoding reliability under varying channel conditions
2Adaptability or versatility
If frequency deviations between transmitting and receiving terminals occur, then system flexibility is improved, but inconsistent sending and receiving criteria result in error codes
Solution Approach 1:
The patent applies dynamics by making the duty cycle adjustment amount variable rather than fixed. The circuit dynamically adapts the adjustment parameter based on the actual frequency deviation and duty cycle characteristics of the received signal, allowing the system to maintain coding accuracy across different operating conditions while preserving system flexibility
3Adaptability or versatility
If direct-current biases are superimposed on BMC waveforms during analog-to-digital conversion, then conversion flexibility is improved, but the signal to noise ratio deteriorates and waveform duty cycle is severely distorted
Solution Approach 1:
The patent extracts and removes the harmful direct-current bias component from the BMC waveform before duty cycle measurement. The adjustment circuit separates the DC offset from the signal and compensates for it, isolating the useful signal components and preventing duty cycle distortion, thereby improving measurement precision while maintaining conversion flexibility
Data Source
AI summary
The present invention relates to a signal duty cycle adaptive-adjustment circuit and method for a receiving terminal. In one embodiment, the circuit includes an analog level comparison circuit, a preprocessing circuit, a first path switch, a second path switch, a decoding circuit, a parameter extraction and estimation circuit, an error generation circuit, a filter feedback circuit and a digital-to-analog conversion circuit. The analog level comparison circuit receives a valid signal according to a reference level to generate a duty cycle signal. The preprocessing circuit preprocesses the duty cycle signal. When the first path switch is turned on, the parameter extraction and estimation circuit acquires duty cycle information from the duty cycle signal to generate a duty cycle deviation. The error generation circuit processes the duty cycle deviation to generate an error signal. The filter feedback circuit and the digital-to-analog conversion circuit filter the error signal and then convert the error signal into an analog voltage signal, which is connected to the analog level comparison circuit to serve as a reference level. When the second path switch is turned on, the decoding circuit decodes the duty cycle signal.