Adaptive Body Biasing in Row Decoders for Latch-Up Prevention
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Solution Overview
Problem
Miniaturization of semiconductor devices, such as image sensors, faces challenges with latch-up issues due to the limitations of traditional transistor biasing methods, which are not amenable to further miniaturization and can lead to device performance and reliability problems.
Innovation Solution
An adaptive body biasing circuit that dynamically couples either a high or low reference voltage to the body terminals of row address decode circuits based on the operating state and relative voltage levels of the reference sources, preventing latch-up by ensuring the body terminals are not biased below a certain voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional transistor biasing methods are used, then device structure is simple, but latch-up occurs leading to poor reliability
Solution Approach 1:
The patent implements dynamic body biasing by switching between a first reference voltage (higher) and a second reference voltage (lower) based on the operating state of the image sensor. During active mode, the higher reference voltage is applied to the body terminal to prevent latch-up, while during sleep mode, the lower reference voltage is applied to reduce power consumption. This dynamic adjustment resolves the contradiction by adapting the biasing strategy to different operational requirements.
Solution Approach 2:
The patent changes the voltage parameter applied to the body terminal based on operating conditions. A voltage switching circuit monitors the operating state and selectively connects either the first reference voltage or the second reference voltage to the body terminal. This parameter change approach allows the system to maintain reliability during active operation while reducing power consumption during sleep mode, without requiring a completely complex circuit architecture.
2Volume of moving object
If miniaturization is pursued, then device size is reduced, but latch-up susceptibility increases
Solution Approach 1:
The patent applies different voltage levels to different operational states locally. During active mode, the body terminal receives a higher reference voltage that creates sufficient potential difference to prevent parasitic transistor activation and latch-up, even in miniaturized structures. During sleep mode, a lower voltage is applied to reduce power consumption. This local quality differentiation allows miniaturization while maintaining latch-up resistance during critical active operation.
Solution Approach 2:
The dynamic switching between reference voltages based on operating state allows the miniaturized device to maintain adequate latch-up protection during active mode when the higher reference voltage is applied, while accepting reduced protection during sleep mode where power consumption is prioritized. The control circuit monitors the operating state and adjusts the body bias accordingly, enabling miniaturization without sacrificing active-mode reliability.
3Use of energy by moving object
If body terminal voltage is reduced, then power consumption is lowered, but latch-up risk increases
Solution Approach 1:
The patent dynamically adjusts the body terminal voltage based on the operating state. During active mode, the first reference voltage (higher) is applied to prevent latch-up, ensuring reliability. During sleep mode, the second reference voltage (lower) is applied to reduce power consumption. The voltage switching circuit controlled by the control circuit enables this dynamic adjustment, resolving the contradiction between power consumption and latch-up prevention by applying the appropriate voltage level at the appropriate time.
Solution Approach 2:
The patent employs periodic switching between different reference voltages corresponding to different operational modes (active and sleep). The control circuit transitions between modes based on operational requirements, and the voltage switching circuit accordingly switches between the first and second reference voltages. This periodic action allows the system to optimize for reliability during active operation and for power consumption during sleep operation, effectively managing the trade-off between these two parameters.
Data Source
AI summary
Techniques and methods for reducing or preventing latch up in row decoder circuits are disclosed herein. An example apparatus may include an array of pixels, a row address decoder, and control circuitry. The row decode circuit including a plurality of decode circuits, each including at least two transistors having respective body terminals coupled to a first node. The control circuitry including a body biasing circuit coupled to the first node, the body biasing circuit to adaptively provide a bias voltage to the first node in response to an operating state of the imaging system and/or a change in one of two reference voltages based on a control signal provided by a bias control circuit.