Adaptive Buffer for Flash Storage Systems

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Solution Overview

Problem

Modern data storage systems face inefficiencies in data reliability and access efficiency due to heterogeneous types of data and/or heterogeneous memory types and sizes, leading to sub-optimal operation.

Innovation Solution

The proposed storage systems optimize write paths for multiple types of data and conditions, incorporating multiple modes for data write paths, including writing to non-storage class memory and then to storage class memory, and bypassing non-storage class memory to directly write to storage class memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single data reliability scheme and data access scheme are used for all types of data and memory configurations, then the system is simple to operate, but the system performance becomes sub-optimal for heterogeneous data types and memory combinations

Engineering Contradiction:
Improveadaptability to different data types and memory configurationsVSAvoidcomplexity of multiple write paths and modes
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically selects between different write paths (Mode 1 and Mode 2) based on real-time conditions such as data type, memory availability, and system state. This dynamic adaptation allows the storage system to optimize performance for heterogeneous data types and memory configurations without requiring manual configuration, resolving the contradiction between adaptability and complexity by making the system flexible and condition-responsive

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (write path selection, buffer allocation, memory usage) based on detected conditions. By monitoring system state and adjusting parameters dynamically, the system achieves high adaptability to different data types and memory configurations while maintaining a unified control interface that masks the underlying complexity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If data is written to non-storage class memory first and then to storage class memory, then data reliability is improved, but write speed and access efficiency may be reduced

Engineering Contradiction:
Improvedata reliabilityVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system dynamically switches between Mode 1 (buffered write through non-storage class memory) and Mode 2 (direct write to storage class memory) based on data type, memory availability, and performance requirements. For reliability-critical data, Mode 1 ensures data is persisted to durable storage, while for performance-critical operations, Mode 2 provides direct fast path writes, resolving the speed-reliability tradeoff through conditional optimization

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Non-storage class memory acts as an intermediary buffer in Mode 1, temporarily holding data before writing to storage class memory. This intermediary layer provides reliability by ensuring data is committed to durable storage while allowing the system to manage write operations in batches, improving overall write efficiency compared to immediate sequential writes

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If data is directly written to storage class memory bypassing non-storage class memory, then write speed is improved, but data reliability may be compromised

Engineering Contradiction:
Improvewrite speedVSAvoiddata reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system selects Mode 2 (direct write) only when conditions permit - such as when data type allows, sufficient storage class memory is available, and reliability requirements are met. This dynamic selection ensures high write speed when safe, while falling back to Mode 1 for reliability-critical operations, resolving the speed-reliability contradiction through context-aware optimization

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250199717A1Adaptive buffer for managed flash system
Publication Date: 2025.06.19 PURE STORAGE INC
  • US20250199717A1 patent drawing
  • US20250199717A1 patent drawing
  • US20250199717A1 patent drawing

AI summary

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.