Adaptive Buffer Queue Processing for SIMD Throughput and Low Delay

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Solution Overview

Problem

Compute devices face challenges in determining the optimal processing strategy for multiple buffers, as they often need to decide between processing a single buffer versus multiple buffers efficiently, leading to inefficiencies in resource utilization and processing time.

Innovation Solution

The implementation of a compute device with adaptive processing capabilities that dynamically determines the most efficient algorithm and processing method based on the number of buffers in the queue, using SIMD instructions for parallel processing when appropriate and SISD instructions for single or multiple buffers to maximize throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the compute device waits for additional buffers before processing, then parallel processing throughput is improved, but processing delay increases

Engineering Contradiction:
Improveparallel processing throughputVSAvoidprocessing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically adjusts processing mode between SISD and SIMD based on the number of available buffers in the queue. When multiple buffers are available, it switches to SIMD parallel processing to maximize throughput; when only one buffer is available, it uses SISD to avoid unnecessary waiting, thereby adaptively optimizing the trade-off between throughput and delay

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the processing parameter (instruction type) based on buffer queue depth. By monitoring the number of buffers and adjusting the processing mode accordingly, the system optimizes performance metrics dynamically rather than using a fixed processing approach

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the compute device immediately processes a single buffer, then processing delay is reduced, but parallel processing efficiency is lost

Engineering Contradiction:
Improveprocessing delayVSAvoidparallel processing throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The system dynamically selects between immediate SISD processing and buffered SIMD processing based on real-time buffer availability. This dynamic decision-making allows the system to avoid unnecessary delays when parallel processing isn't possible while still capturing parallel efficiency when multiple buffers are available

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The processing mode parameter is changed based on the buffer queue state. The system transitions between processing modes (SISD vs SIMD) according to the number of available buffers, optimizing the balance between response time and throughput

Inventive Principle:
Principle #35Parameter changes

3Productivity

If SIMD instructions are used for all buffers, then parallel processing capability is maximized, but processing overhead increases for small buffer counts

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidprocessing overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention segments the processing approach based on buffer quantity. Instead of applying a uniform SIMD approach to all buffer counts, it divides the processing strategy into SISD for single buffers and SIMD for multiple buffers, reducing unnecessary overhead for small buffer counts while maintaining parallel capability when appropriate

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3488338B1Technologies for adaptive processing of multiple buffers
Publication Date: 2024.04.17 INTEL CORP
  • EP3488338B1 patent drawingFigure 1
  • EP3488338B1 patent drawingFigure 2
  • EP3488338B1 patent drawingFigure 3

AI summary

Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.