Adaptive Bus Addressing for Efficient Register Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bus protocols are inefficient for accessing narrow targets like registers due to their wide width design, leading to reduced effective bandwidth and performance.
Innovation Solution
An adaptive bus protocol that allows for dynamic adjustment of address and data width, enabling efficient access to multiple registers through modes such as pack and multi-mode, utilizing processing circuitry and bus interfaces to generate and transmit short addresses for special function registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a wide bus width is used to meet high bandwidth demand, then memory access bandwidth is improved, but efficiency for accessing narrow targets like registers deteriorates
Solution Approach 1:
The bus protocol dynamically adjusts its operation mode based on the access target type. When accessing special function registers, it switches to a mode that generates multiple short addresses corresponding to different register banks, optimizing for narrow target access. When accessing general memory, it uses the full wide bus capability for high bandwidth. This dynamic adaptation resolves the contradiction by allowing the system to optimize for either bandwidth or access efficiency depending on the specific access requirement.
Solution Approach 2:
The invention changes the address generation parameters based on the access mode. In register access mode, the bus interface generates multiple short addresses (e.g., 8-bit addresses) instead of using the full wide address bus, and structures data transfers in packed formats. This parameter change allows efficient access to narrow register targets while maintaining the physical wide bus infrastructure for when it is needed.
2Device complexity
If a single address is used for bus access, then address simplicity is improved, but the ability to access multiple special function registers efficiently deteriorates
Solution Approach 1:
The address space is segmented into multiple register banks, each accessible via short addresses. The bus interface unit generates multiple short addresses that map to different segments (register banks) of the special function register space. This segmentation allows efficient access to multiple registers by breaking down the address space into manageable chunks that can be accessed in parallel or sequential batches, improving register access speed without complicating the overall address structure.
Solution Approach 2:
The address structure uses a nested approach where a base address identifies the register bank, and short addresses identify specific registers within that bank. This nested addressing allows the system to efficiently access multiple registers by combining the base address with offset addresses, effectively creating a hierarchical address structure that improves access speed while maintaining address simplicity at each level.
Data Source
AI summary
Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.