Adaptive Cache Monitoring for DDIO Oversubscription Control
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Solution Overview
Problem
In modern enterprise computing environments, existing cache monitoring systems struggle to accurately differentiate between cache eviction due to oversubscription and cache consumption, leading to inefficient data handling and increased latency and energy consumption, particularly in non-inclusive cache hierarchies where single LLC occupancy counters fail to provide a full picture of cache utilization.
Innovation Solution
The implementation of a cache monitor with three separate counters (La, Lp, and Le) per Resource Monitoring ID (RMID) to track cache allocation, processing, and eviction, allowing for a more accurate direct write policy to be determined, enabling adaptive Data Direct I/O (DDIO) that directs data to the last-level cache when space is available and writes to memory when the cache is oversubscribed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single LLC occupancy counter is used to monitor cache utilization, then the monitoring system is simple, but it fails to accurately differentiate between cache eviction due to oversubscription and cache consumption
Solution Approach 1:
The patent segments the single occupancy counter into three separate counters: La (allocation counter) that increments when cache lines are allocated to the LLC, Lp (processing counter) that increments when cache lines are processed by the CPU, and Le (eviction counter) that increments when cache lines are evicted. This segmentation allows accurate differentiation between cache allocation, processing, and eviction events, enabling precise monitoring of cache utilization without oversimplification.
2Productivity
If data is always written to the last-level cache via Device Direct I/O, then I/O performance is improved, but unnecessary cache evictions occur when the cache is oversubscribed
Solution Approach 1:
The patent implements a feedback mechanism where the monitoring logic continuously tracks the values of La, Lp, and Le counters and compares them to determine the current cache state. Based on this feedback, the system dynamically adjusts the write policy: when La > Lp (indicating oversubscription), data is written directly to system memory; when La ≤ Lp (indicating available capacity), data is written to the LLC via DDIO. This feedback loop ensures optimal I/O performance while preventing unnecessary cache evictions.
3Measurement precision
If the cache monitor uses three separate counters per RMID, then accurate cache state determination is achieved, but the monitoring system complexity increases
Solution Approach 1:
The patent merges the functionality of three separate counters into a unified monitoring logic that operates within the cache controller. The monitoring logic receives cache access requests, determines the RMID from each request, and updates the appropriate counters (La, Lp, or Le) based on the access type. This merging approach maintains measurement precision while reducing implementation complexity compared to three completely independent monitoring systems.
Data Source
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AI summary
There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.