Adaptive Cache Memory Reconfiguration for Ultra-Low Voltage Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computer memories set a conservative minimum supply voltage that restricts other circuit components from operating at lower voltages, limiting power savings and performance, as the minimum voltage is dictated by the memory's failure point, even though not all memory cells fail simultaneously.
Innovation Solution
An adaptive memory system that allows operation below the conventional minimum supply voltage by dynamically re-configuring the cache memory based on power and performance requirements, using a Memory Management Unit to determine the usable percentage of memory cells and adjust error correction mechanisms, enabling reduced power consumption while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the minimum memory supply voltage is set conservatively to ensure all memory cells operate reliably, then memory reliability is improved, but power consumption increases and other circuit components cannot operate at lower voltages
Solution Approach 1:
The patent applies dynamics by making the memory configuration adaptive and changeable based on operating conditions. The Memory Management Unit dynamically reconfigures the memory array by enabling or disabling specific memory cells based on the supply voltage level, allowing the system to transition between different operational states rather than being fixed at a conservative voltage threshold
Solution Approach 2:
The patent changes the operational parameters of memory cells based on supply voltage conditions. By monitoring the supply voltage and adjusting which memory cells are active, the system adapts to different voltage levels and maintains reliability while enabling lower power consumption modes when voltage is reduced
2Reliability
If the minimum memory supply voltage is set conservatively to prevent bitcell failure, then memory reliability is improved, but the minimum supply voltage for the overall integrated circuit is increased, preventing other components from operating at lower voltages
Solution Approach 1:
The patent segments the memory array into multiple independently controllable sections or memory cells. The Memory Management Unit can selectively enable or disable specific segments based on the supply voltage level, allowing different parts of the memory to operate at different effective thresholds and enabling the system to function at lower overall voltage levels
Solution Approach 2:
The system dynamically adjusts which memory cells are active based on real-time voltage monitoring, allowing the integrated circuit to adapt its voltage operating range and enabling other components to operate at lower voltages when the memory operates in a reduced-voltage mode
3Reliability
If error correction mechanisms are strengthened to maintain reliability at lower voltages, then memory reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback by having the Memory Management Unit monitor the supply voltage level and use this information to dynamically adjust memory configuration and error correction settings. This feedback loop allows the system to maintain reliability at lower voltages by adaptively strengthening error correction only when and where needed, rather than using fixed complex error correction throughout
Solution Approach 2:
The system changes error correction parameters dynamically based on operating conditions. By adjusting error correction strength according to the supply voltage level and which memory cells are active, the system maintains reliability while avoiding the constant complexity of maximum-strength error correction
Data Source
AI summary
Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).