Adaptive Cache Sleep Control for Leakage Reduction
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Solution Overview
Problem
In multicore processors, conventional static sleep settings for cache memory do not effectively account for process, voltage, and temperature variations across the die, leading to suboptimal power savings due to varying leakage power consumption.
Innovation Solution
Implementing a dynamic and independent calculation of sleep settings for each cache slice based on local process, voltage, and temperature conditions, using a power controller to determine optimal sleep settings and adjust the sleep circuitry accordingly, allowing each cache slice to enter a sleep state closer to its retention voltage and thereby maximize leakage power savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If static sleep settings are used for cache memory, then device complexity is reduced, but power savings are suboptimal due to PVT variations
Solution Approach 1:
The cache memory is divided into multiple independently controllable slices, each with its own sleep control mechanism. This segmentation allows each slice to be optimized individually based on local PVT conditions, maximizing power savings while maintaining manageable complexity through modular control
Solution Approach 2:
Each cache slice is equipped with local sensors that monitor process, voltage, and temperature conditions specific to that region. The sleep settings are then adjusted locally based on these measurements, ensuring optimal power savings for each slice without requiring global control complexity
2Loss of energy
If dynamic sleep settings are implemented for each cache slice, then power savings are optimized, but device complexity increases
Solution Approach 1:
Each cache slice autonomously monitors its own PVT conditions through local sensors and automatically adjusts its sleep settings based on predefined criteria. This self-service approach eliminates the need for complex centralized control logic, reducing overall device complexity while maintaining dynamic optimization
Solution Approach 2:
The system dynamically changes the sleep parameters (such as sleep voltage and timing) based on measured PVT conditions. By adjusting these parameters in response to environmental variations, the system achieves optimal power savings without requiring complex control mechanisms
3Loss of energy
If sleep voltage is reduced to maximize leakage savings, then power consumption decreases, but retention reliability may be compromised
Solution Approach 1:
Local sensors continuously monitor the actual PVT conditions in each cache slice and provide feedback to the sleep control mechanism. This feedback enables the system to adjust sleep voltage dynamically, ensuring it remains high enough to maintain data retention reliability while still achieving maximum leakage savings under varying conditions
Solution Approach 2:
The sleep voltage is made dynamic rather than static, allowing it to be adjusted in real-time based on measured PVT conditions. This dynamic adjustment ensures that the voltage remains sufficient for reliable data retention when needed, while allowing greater voltage reduction when conditions permit, thus balancing reliability and power savings
Data Source
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AI summary
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.