Adaptive-Threshold Capacitive Logic Gate for Lower Transistor Count

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Solution Overview

Problem

Existing circuit architectures for multi-input logic gates consume high power due to the increasing number of transistors, which poses a challenge for reducing power consumption, especially in battery-powered devices.

Innovation Solution

A capacitive input circuit that can be programmed to perform different logic functions by adjusting the switching threshold, using a pull-up and pull-down device coupled to a summing node, allowing for configuration as various logic gates such as AND/NAND, OR/NOR, and others.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If traditional logic gate architecture is used, then logic functions can be implemented, but power consumption increases due to increasing number of transistors

Engineering Contradiction:
Improvepower consumptionVSAvoidnumber of transistors
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

Multiple logic gate functions (AND, OR, NAND, NOR) are merged into a single capacitive circuit by dynamically reconfiguring the switching threshold through control signals. The same physical circuit structure performs multiple logic operations by adjusting the reference voltage level, eliminating the need for separate transistor networks for each logic gate type.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The capacitive circuit is designed as a universal logic gate that can perform different logic functions (AND, OR, NAND, NOR) by changing the switching threshold. This multi-functional approach allows a single circuit to replace multiple dedicated logic gates, significantly reducing the total transistor count while maintaining full logic functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more transistors are used to implement multi-input logic gates, then more logic functions can be achieved, but power consumption increases

Engineering Contradiction:
Improvelogic function capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The circuit achieves universal logic function capability through dynamic threshold reconfiguration. By adjusting the reference voltage level using control signals, the same capacitive circuit can implement AND, OR, NAND, and NOR functions, providing adaptability without requiring additional transistors for each logic type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The switching threshold parameter is dynamically changed through control signals that adjust the reference voltage level. This parameter modification allows the circuit to adapt between different logic functions without structural changes, maintaining versatility while minimizing power consumption by using the same physical components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12334918B1Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold
Publication Date: 2025.06.17 KEPLER COMPUTING INC
  • US12334918B1 patent drawing
  • US12334918B1 patent drawing
  • US12334918B1 patent drawing

AI summary

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.