Adaptive Capacitors with In-Line Measurement and Vertical Stacking
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Solution Overview
Problem
Existing methods for controlling capacitor values in integrated circuits, such as power amplifier circuits, face challenges in achieving precise capacitance tolerance within 3% due to variations, especially in stacked capacitors, which require additional layout area and increased costs, and cannot be measured before process wiring is completed.
Innovation Solution
The method involves forming a bottom plate in a first metal layer, a middle plate in a second layer, and measuring the capacitance to determine if additional capacitors should be coupled in parallel to adjust the capacitance, allowing for in-line correction and reduced layout area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitors are wired in parallel to control capacitance value, then capacitance precision is improved, but layout area increases
Solution Approach 1:
The patent transitions from planar parallel wiring to vertical stacking by utilizing multiple metal layers (first, second, and third metal layers) to form capacitors at different heights. This dimensional change allows capacitance adjustment without increasing lateral layout area, as capacitors are stacked vertically rather than placed side-by-side.
Solution Approach 2:
The patent implements nested capacitor structures where capacitors in different metal layers are vertically aligned and electrically connected through conductive vias. The first capacitor in the first metal layer is nested with the second capacitor in the second metal layer, allowing them to function as a combined capacitance element while occupying the same footprint area.
2Area of stationary object
If stacked capacitors are used, then layout area is reduced, but measurement before wiring cannot be performed
Solution Approach 1:
The patent performs capacitance measurement of the first capacitor before completing the wiring process and formation of subsequent capacitors. This preliminary measurement allows the system to determine the actual capacitance value early in the manufacturing process, enabling corrective actions to be taken before final assembly is complete.
Solution Approach 2:
The patent implements a feedback mechanism where the measured capacitance value of the first capacitor is used to determine whether to form and connect additional capacitors in parallel. If the measured value is outside the acceptable tolerance range, the system responds by adding compensating capacitance through additional capacitors, thereby correcting the total capacitance to meet specifications.
3Manufacturing precision
If additional metal layers are added for capacitor wiring, then capacitance control is improved, but manufacturing cost increases
Solution Approach 1:
The patent integrates capacitor formation into the existing multi-layer metal infrastructure already required for circuit interconnections. The same metal layers and via structures used for signal routing are also utilized to form and connect capacitor elements, thereby achieving capacitance control without adding dedicated additional process steps or specialized structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of capacitance values within a 3% tolerance by measuring and adjusting the capacitance before the deposition of additional capacitors, improving yield and reducing the need for additional layout space and costly process improvements.
Implementation Method 1
a first capacitor with a first capacitance... measuring the capacitance of the first capacitor... a second capacitor with a second capacitance, and the third capacitor with a third capacitance
Implementation Method 2
providing a first dielectric material over the bottom plate... providing a second dielectric material over the middle plate
Data Source
AI summary
A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.