Adaptive Cascode Circuit for High-Voltage MOS Transistors
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Solution Overview
Problem
Conventional cascode circuits using MOS transistors are limited by their maximum withstand voltage, making them unsuitable for high-voltage applications and requiring costly MOS transistors with high withstand voltages, while the maximum withstand voltage is often restricted by semiconductor processes.
Innovation Solution
An adaptive cascode circuit is designed with a main MOS transistor and n series-coupled adaptive MOS transistors, utilizing shutdown and conduction clamping circuits to control drain-gate voltages and ensure they do not exceed rated voltages, allowing for a higher equivalent withstand voltage and enabling all MOS transistors to be controlled by a single signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional cascode circuits use MOS transistors to improve output impedance, then the output impedance increases, but the maximum withstand voltage remains limited by semiconductor processes
Solution Approach 1:
The patent divides a single high-voltage MOS transistor into multiple lower-voltage MOS transistors connected in series. Each transistor handles a portion of the total voltage, allowing the circuit to achieve high withstand voltage capability without requiring expensive high-voltage transistors. The segmentation principle is applied by creating a stack of n adaptive MOS transistors where the total withstand voltage is the sum of individual transistor ratings.
Solution Approach 2:
The patent implements dynamic control of the cascode transistors through adaptive gating signals that adjust the conduction state of each transistor in the stack. The shutdown clamping circuit dynamically responds to voltage conditions to prevent excessive drain-gate voltages, while conduction clamping circuits dynamically control the turn-on behavior. This dynamic adaptation allows the circuit to maintain high output impedance while safely handling high voltages.
2Reliability
If high voltage MOS transistors are selected for high voltage applications, then the withstand voltage requirement is met, but the cost increases significantly
Solution Approach 1:
The patent segments the high-voltage requirement across multiple standard-voltage transistors, eliminating the need for expensive high-voltage MOS transistors. By using n transistors with lower individual voltage ratings, the circuit achieves the required total withstand voltage using cheaper, more readily available components from standard semiconductor processes.
Solution Approach 2:
The patent changes the voltage distribution parameters by distributing the total voltage stress across multiple transistors rather than concentrating it on a single device. The shutdown clamping circuit enforces parameter limits on individual drain-gate voltages, ensuring each transistor operates within its safe operating range while collectively handling higher voltages.
3Reliability
If multiple MOS transistors are coupled in series to increase withstand voltage, then the equivalent withstand voltage increases, but the circuit complexity increases
Solution Approach 1:
The patent makes each transistor in the stack multi-functional by equipping them with both shutdown clamping protection and conduction clamping control. The adaptive gating signals serve multiple purposes: they control conduction timing and provide voltage clamping. This universality reduces the need for separate dedicated clamping circuits for each transistor, thereby managing complexity while achieving high withstand voltage.
Solution Approach 2:
The patent implements feedback mechanisms through the shutdown clamping circuit that monitors drain-gate voltages and provides corrective action when voltage limits are approached. The conduction clamping circuits also use feedback from voltage conditions to control the turn-on behavior of each transistor. This feedback control automates the management of the multi-transistor stack, reducing the complexity of manual design and adjustment.
4Ease of operation
If conventional cascode circuits are used, then the output current is not affected by output voltage, but the circuit is limited to low voltage applications
Solution Approach 1:
The patent segments the voltage handling capability across multiple transistors, enabling the circuit to operate in high-voltage applications while maintaining the current stability characteristic of conventional cascode circuits. Each transistor in the series stack handles a portion of the voltage, allowing the overall circuit to achieve both current independence from voltage and adaptability to high-voltage environments.
Solution Approach 2:
The patent introduces dynamic control mechanisms that adapt the conduction behavior of each transistor based on real-time voltage conditions. The adaptive gating signals and clamping circuits dynamically adjust to maintain proper cascode operation across a wide voltage range, enabling the circuit to preserve output current stability while operating in high-voltage applications where conventional fixed-bias cascode circuits would fail.
Data Source
AI summary
The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.