Adaptive Cascode Power Amplifier for Linearity and Quiescent Current
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Solution Overview
Problem
Class AB power amplifiers face challenges in achieving high linearity and low current consumption, particularly at high output power levels, due to inefficiencies and increased quiescent current, which are not optimized in existing designs.
Innovation Solution
A power amplifier circuit with adaptive cascode structures and variable transistor size, utilizing sensing mechanisms and control circuits to adjust transistor size based on output power, combining Class AB and Class A amplification to optimize efficiency and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the transistor is oversized to generate high output power, then the output power capability is improved, but the quiescent current increases and efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the transistor size adjustable rather than fixed. A control circuit dynamically selects between different transistor sizes (first and second transistors with different dimensions) based on the required output power level. This allows the amplifier to use a smaller transistor for low power consumption when high output power is not needed, and switch to a larger transistor when high output power is required, thus resolving the contradiction between output power capability and quiescent current consumption.
2Power
If the transistor is oversized to generate high output power, then the output power capability is improved, but the linearity deteriorates due to excessive capacitance
Solution Approach 1:
The patent uses dynamics to adjust transistor size based on operating conditions. By switching between a first transistor and a second transistor with different sizes, the system maintains optimal linearity characteristics. When operating at lower power levels where linearity is critical, the smaller transistor is used which has lower parasitic capacitance. This dynamic adaptation prevents the linearity deterioration that would occur with a permanently oversized transistor.
3Use of energy by moving object
If the transistor is undersized to minimize quiescent current, then the power consumption is reduced, but the output power capability deteriorates
Solution Approach 1:
The patent resolves this contradiction through dynamic transistor size selection. The control circuit monitors the required output power and switches between a first transistor (smaller size for low power consumption) and a second transistor (larger size for high output power capability). This allows the system to minimize power consumption during normal operation by using the smaller transistor, while still maintaining the capability to deliver high output power when needed by switching to the larger transistor.
4Device complexity
If a single transistor size is used, then the device complexity is reduced, but the adaptability to different power levels deteriorates
Solution Approach 1:
The patent applies dynamics by implementing a control circuit that dynamically selects between different transistor configurations based on the required output power level. The control circuit receives information about the desired power output and switches between a first transistor and a second transistor with different sizes. This dynamic adaptation provides versatility across different power levels while keeping the additional complexity manageable through a relatively simple switching mechanism.
Data Source
Figure 1
Figure 2a~2b
Figure 3a~3b
AI summary
A Power amplifier circuit comprising an input (100), an output (700) comprising; - means for sensing (131, 132, 133) the input voltage; - a set of n cascode circuits, each comprising a first transistor (110-1, 110-2, ... 110-n) having a gate, a source and a drain terminal and further comprising a second transistor (120-1, 120-2, ... 120-n) having gate, source and drain terminal; the source and gate of the first transistor of said cascode circuits being respectively connected to a first reference voltage (GND) and to receive the input signal (RFin), the drain of said first transistor being connected to the source of said second transistor, the drain of which being coupled to said output (700); - a control ciurcuit (150) receiving the input voltage sensed by said sensing means (131, 132, 133) for generating a set of control signals which are transmitted to the gate of the second transistor of said n cascode circuits; By activating or disactivating one or more of the n cascode circuits, the total size of the amplification components can be adapted to the value of the output power to generate.