Adaptive Clamping Voltage Scheme for Multi-Level Neural Network Computing
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Solution Overview
Problem
Conventional memory units face challenges in increasing computing information in one cycle while minimizing errors due to overlapping currents, which affects the accuracy and power consumption in multi-level neural network based computing-in-memory applications.
Innovation Solution
A memory unit with an adaptive clamping voltage scheme and calibration scheme, utilizing a clamping module with a clamping transistor, cell detector, and clamping control circuit to adjust bit-line currents based on reference and bit-line clamping voltages, allowing for multiple input bits in one cycle and reducing interference between memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple operation cycles are used to generate multi-bit input, then the accuracy of computing results is improved, but the operation speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the actual computing operation. This preliminary voltage setup enables the bit line to directly accommodate multi-bit input currents in a single operation cycle, eliminating the need for multiple sequential operation cycles and thereby improving operation speed while maintaining computational accuracy
2Speed
If the amount of operation information is increased in one operation cycle to increase operation speed, then the operation speed is improved, but the accuracy of computing results deteriorates due to overlapping currents
Solution Approach 1:
The patent introduces an intermediary mechanism - the bit line with pre-charged voltage - that acts as a mediator between multiple memory cell currents and the sense amplifier. This intermediary bit line absorbs and separates the overlapping currents from multiple memory cells, preventing direct interference while enabling parallel processing of multiple operation bits in one cycle, thus maintaining both high speed and high accuracy
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the voltage level of the bit line based on the number of active memory cells and the amount of operation information. By changing the bit line voltage parameter adaptively, the system can accommodate varying amounts of parallel computing information without suffering from current overlapping errors, enabling high-speed multi-bit operations with maintained precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the accuracy and reduces power consumption by generating different bit-line currents using adaptive clamping voltages, improving the utilization rate of memory cells and minimizing errors caused by overlapping currents.
Implementation Method 1
The bit-line current is flowed through the clamping transistor, and the clamping transistor is controlled by the bit-line clamping voltage to adjust the bit-line current
Implementation Method 2
The cell detector is configured to detect the bit-line current to generate a comparison output according to the reference voltage
Data Source
AI summary
A memory unit is controlled by a word line, a reference voltage and a bit-line clamping voltage. A non-volatile memory cell is controlled by the word line and stores a weight. A clamping module is electrically connected to the non-volatile memory cell via a bit line and controlled by the reference voltage and the bit-line clamping voltage. A clamping transistor of the clamping module is controlled by the bit-line clamping voltage to adjust a bit-line current. A cell detector of the clamping module is configured to detect the bit-line current to generate a comparison output according to the reference voltage. A clamping control circuit of the clamping module switches the clamping transistor according to the comparison output and the bit-line clamping voltage. When the clamping transistor is turned on by the clamping control circuit, the bit-line current is corresponding to the bit-line clamping voltage multiplied by the weight.