Adaptive Clock Domain Alignment in Packet Networks
Solution Overview
Problem
Current methods for aligning clock domains in packet networks are inadequate, as they either require expensive hardware, are slow to achieve synchronization, or are not suitable for networks without physical broadcast channels, leading to delays and errors in telecommunication applications.
Innovation Solution
An adaptive method that estimates packet delays, sends time-stamped synchronization packets, weights data points based on delay, and continuously updates the delay estimate to align clock domains over asynchronous networks, allowing for rapid and precise frequency and phase synchronization without the need for physical broadcast channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Plesiochronous mode is used to transport clock over packet network, then hardware costs are reduced, but time synchronization accuracy deteriorates and slips occur
Solution Approach 1:
The patent implements a feedback mechanism where the receiving端 measures the actual arrival time of packets and compares it with the expected arrival time based on timestamps. This feedback information is used to adjust the local clock frequency and phase, enabling automatic compensation for timing deviations without requiring expensive shared clock hardware
Solution Approach 2:
The patent replaces the mechanical/shared clock distribution system with a software-based timestamp and measurement system. Instead of physically distributing a shared clock signal through expensive wiring and GPS receivers, the system uses packet timestamps and software algorithms to achieve synchronization
2Device complexity
If Adaptive Clock Recovery (ACR) is used to transport clock over packet network, then hardware requirements are reduced, but synchronization accuracy is insufficient to meet telecommunication standards
Solution Approach 1:
The patent enhances ACR by implementing a precise feedback loop where the receiving端 continuously measures packet arrival times using local timestamps, calculates the deviation from expected arrival times, and uses this feedback to adjust the local clock. This feedback mechanism enables the system to achieve the required 50-20 ns accuracy
Solution Approach 2:
The patent applies preliminary actions by pre-calculating expected packet arrival times based on transmission timestamps and network conditions. This allows the system to proactively compensate for anticipated delays and jitter before they affect synchronization, rather than merely reacting to deviations
3Measurement precision
If shared clock method is used for clock transport, then synchronization accuracy is improved, but hardware costs and complexity increase due to GPS receivers and wiring
Solution Approach 1:
The patent uses timestamp copying where the transmission time of clock signals is recorded as a timestamp in each packet. The receiving端 copies this timestamp information and uses it to reconstruct the original clock timing, eliminating the need for physical shared clock infrastructure
Solution Approach 2:
The patent substitutes the mechanical shared clock distribution system (GPS receivers, synchronized wiring) with a software-based timestamp system that runs over standard packet networks, dramatically reducing hardware requirements while maintaining synchronization accuracy
4Measurement precision
If packet arrival rate is increased to improve time recovery accuracy, then measurement precision is improved, but network bandwidth consumption increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating the expected arrival times of packets based on transmission timestamps and network conditions. This allows the system to achieve accurate time recovery with fewer packets, as each packet carries pre-computed timing information that can be directly used for synchronization
Solution Approach 2:
The patent changes the parameter of packet timing information by embedding precise timestamps in each packet and using weighted averaging of arrival time deviations. This allows the system to achieve high accuracy with a smaller number of packets compared to methods that rely on increasing packet rates
Data Source
AI summary
Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points. These steps are continually repeated on new sets of data points created from newly received synchronization packets using the current delay estimate for the expected delay. And a clock domain at the destination is continually aligned with a clock domain at the source based on the current delay estimate for packets traversing the network between the source and destination.