Adaptive Clock Delay Line for Fractional Droop-Based Clock Stretching
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Solution Overview
Problem
Conventional clocking circuitry faces performance reduction due to integer-based clock division, leading to timing failures during power supply droops, as it lacks the ability to provide efficient clock stretching with fractional division factors.
Innovation Solution
An adaptive clocking architecture using a delay line as a time base for elastic clock stretching, allowing gate delay-based stretching proportional to the droop, eliminating the need for additional processing power and ADCs, and simplifying the stretching state machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integer-based clock division is used to mitigate droop, then timing failures are prevented, but system performance is greatly reduced due to inability to provide fractional division
Solution Approach 1:
The patent changes the clock division parameter from integer-only to fractional values by introducing a delay line with multiple tap points. This allows the clocking circuit to select different delay amounts (fractional clock periods) based on detected droop magnitude, thereby maintaining timing reliability while minimizing performance impact through precise, adjustable stretching.
Solution Approach 2:
The system dynamically adjusts the clock stretching amount by selecting different tap points in the delay line based on real-time droop detection. This dynamic adaptation allows the system to apply only the necessary stretching (fractional division) rather than fixed integer division, resolving the contradiction between reliability and performance.
2Reliability
If clock stretching is triggered frequently to prevent timing failures, then timing reliability improves, but energy consumption increases due to excessive stretching operations
Solution Approach 1:
The patent enables precise control of stretching magnitude through fractional division factors selected from multiple tap points in the delay line. By adjusting the stretching parameter to match the actual droop magnitude, the system prevents over-stretching and reduces unnecessary energy consumption while maintaining timing reliability.
Solution Approach 2:
The system applies partial stretching (only the amount needed to compensate for detected droop) rather than excessive stretching. The delay line provides a range of stretching amounts, allowing the circuit to apply just enough delay to prevent timing failures without unnecessary energy expenditure from excessive stretching.
3Reliability
If traditional digital clock divider is used for droop mitigation, then clock stretching is achieved, but device complexity increases due to additional processing power and ADC requirements
Solution Approach 1:
The delay line is directly connected to the same power supply that experiences droop, allowing it to automatically experience and reflect the droop effect. This self-service mechanism eliminates the need for separate ADCs and complex processing circuits to detect and measure droop, as the delay line inherently provides droop-proportional stretching.
Solution Approach 2:
The delay line acts as an intermediary that directly translates power supply voltage variations into proportional delay variations. This intermediary mechanism simplifies the overall circuit by replacing complex ADC and processing circuits with a passive delay structure that naturally responds to droop conditions.
Data Source
AI summary
Various implementations described herein are related to a device having adaptive clocking architecture with multiple stages of latches and buffers coupled in a delay line configuration. In some instances, each latch receives a delayed clock signal as data input and provides a sample out signal as a latched output based on a clock signal. Also, in some instances, each latch provides a delayed edge of a next clock cycle so as to stretch the pulse width of the clock signal.