Adaptive Clock Duty Cycle Control for Aging Automotive SoCs

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Solution Overview

Problem

Clock distribution networks in automotive systems-on-a-chip (SoCs) experience duty cycle distortion due to PLL variations, systematic design limitations, random hardware faults, and aging, leading to timing issues in circuits.

Innovation Solution

An adaptive clock duty cycle controller (DCC) with duty cycle adjusters (DCAs) and a monitor (DCM) to measure and correct duty cycle distortions, incorporating safety-critical features for compliance with automotive standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If duty cycle adjusters (DCAs) are added to correct duty cycle distortion, then timing reliability is improved, but device complexity increases

Engineering Contradiction:

Improvetiming reliabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where a duty cycle monitor (DCM) continuously measures the actual duty cycle of the clock signal and feeds this information back to the duty cycle adjusters (DCAs). The DCAs then automatically adjust their correction amounts based on the measured duty cycle distortion, creating a closed-loop control system that maintains timing reliability without requiring manual intervention or complex external control circuitry.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The duty cycle correction system is designed to be self-regulating. The monitor circuit automatically detects duty cycle distortion and the adjuster circuits automatically compensate for it without external control. This self-service mechanism reduces the need for additional complex control logic and external intervention, thereby improving reliability while limiting the increase in device complexity.

Inventive Principle:

Principle #25Self-service

2Manufacturing precision

If multiple DCAs are used for comprehensive duty cycle correction, then duty cycle accuracy is improved, but manufacturing complexity increases

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidmanufacturing complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent divides the duty cycle correction function into multiple independent duty cycle adjuster (DCA) units, each responsible for correcting distortion in specific clock signal paths. This segmentation allows each DCA to be designed and manufactured as a standardized module, simplifying the overall manufacturing process while achieving comprehensive duty cycle accuracy across multiple paths through the combined operation of these modular units.

Inventive Principle:

Principle #1Segmentation

3Measurement precision

If a duty cycle monitor (DCM) is implemented to measure DCD, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

ImproveDCD measurement precisionVSAvoiddevice complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines the duty cycle monitor (DCM) and duty cycle adjuster (DCA) functions into an integrated control system where the monitor and adjuster work as a unified unit. This merging reduces the need for separate independent circuits and interfaces, thereby achieving precise DCD measurement while minimizing the overall increase in device complexity through functional integration.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260066882A1Adaptive clock duty cycle controller (DCC) for automotive system-on-a-chip (SOC)

Publication Date: 2026.03.05 QUALCOMM INC

AI summary

Aspects of the present disclosure relate to an adaptive clock duty cycle controller (DCC) in an automotive system-on-a-chip (SoC). The adaptive clock DCC may include one or more devices, which may be configured to measure and adapt a duty cycle of a clock signal to compensate for aging effects on components in a signal path of a clock distribution network.